DS2762BE+T&R Maxim Integrated Products, DS2762BE+T&R Datasheet - Page 23

• Manufacturer Part Number: DS2762BE+T&R
• Description: IC MON BATT LI-ION HP 16-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS2762BE+T&R

• Function: Battery Monitor
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the DS2762
are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data.
The bus master initiates all these types of signaling except the presence pulse.
The initialization sequence required to begin any communication with the DS2762 is shown in Figure 18. A
presence pulse following a reset pulse indicates that the DS2762 is ready to accept a net address command. The
bus master transmits (Tx) a reset pulse for t
(Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin,
the DS2762 waits for t
Figure 18. 1-Wire Initialization Sequence
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be t
in duration with a 1ms minimum recovery time, t
between 15ms and 60ms after the line falls. If the line is high when sampled, a write 1 occurs. If the line is low when
sampled, a write 0 occurs (Figure 19). For the bus master to generate a write 1 time slot, the bus line must be
pulled low and then released, allowing the line to be pulled high within 15ms after the start of the write time slot. For
the host to generate a write 0 time slot, the bus line must be pulled low and held low for the duration of the write-
time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master must keep the bus line low for at least 1ms and then release it to allow the DS2762 to present valid
data. The bus master can then sample the data t
read-time slot, the DS2762 releases the bus line and allows it to be pulled high by the external pullup resistor. All
read-time slots must be t
See Figure 19 for more information.
DQ
LINE TYPE LEGEND:
PDH
SLOT
and then transmits the presence pulse for t
t
(60ms to 120ms) in duration with a 1ms minimum recovery time, t
RSTL
BUS MASTER ACTIVE LOW
BOTH BUS MASTER AND
DS2762 ACTIVE LOW
t
PDH
RSTL
. The bus master then releases the line and goes into receive mode
REC
RDV
, between cycles. The DS2762 samples the 1-Wire bus line
23 of 25
(15ms) from the start of the read-time slot. By the end of the
t
PDL
DS2762 ACTIVE LOW
RESISTOR PULLUP
PDL
t
.
RSTH
REC
SLOT
, between cycles.
(60ms to 120ms)
PACK+
PACK-