ISL6253HAZ-T Intersil, ISL6253HAZ-T Datasheet - Page 19

• Manufacturer Part Number: ISL6253HAZ-T
• Description: IC BATTERY CHRGR NOTEBOOK 28QSOP
• Manufacturer: Intersil

Specifications of ISL6253HAZ-T

• Function: Charge Management
• Battery Type: Lithium-Ion (Li-Ion), Lithium-Polymer (Li-Pol)
• Voltage - Supply: 7 V ~ 25 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 20 shows the type II compensator and its transfer
function is expressed as follows:
where
Compensator design goal:
• High DC gain
• Loop bandwidth f
• Gain margin: >10dB
• Phase margin: 40°
The compensator design procedure is as follows:
The loop gain T
gain. Therefore, the compensator resistance R
determined by:
where g
amplifier. Compensator capacitor C1 is then given by:
Example: V
C
(R
f
Put the compensator zero at 1.7kHz, and put the
compensator pole at esr zero which is 725kHz. The
compensator capacitors are:
C
Such small C
the phase and gain at such high frequency.
A
R
C
c
1. Put compensator zero at
2. Put one compensator pole at zero frequency to achieve
o
1
v
1
1
= 15kHz, then compensator resistance R
cs
( )
= 22µF/10mΩ, L = 15µH, g
= 10nF, C
S
=
high DC gain, and put another compensator pole at either
esr zero frequency or half switching frequency, whichever
is lower.
=
= 25mΩ, A
-----------------
R
2πf
-----------------------------------
=
1
ω
m
1
ω
g
v ˆ
---------------- -
cz
c
cz
comp
m
v ˆ
V
is the trans-conductance of the voltage error
FB
,
in
o
V
=
C
C
FB
2
2
= 20V, V
2
-------------- - ω
R
o
= 22pF
may not be necessary since it does not affect
R
1
v
c
=
=
1
(S) at cross over frequency of f
C
T
= 6), V
-------------------- -
C
----------------------------------------- -
2πR
1
c:
1
,
g
+
m
o
1
cp
C


C
1
-- -
5
= 16.8V, I
C
FB
2
1
=
–
1
f
----------------------------- -
S 1
esr
---------------------- -
R
----- -
30
C
= 2.1V, V
1


1
1
1
19
 f

+
C
–
ω
+
m
+
s
1
--------- -
ω
1
cz
C
--------- -
ω
S
C
= 250µs, R
cz
S
o
cp
2
2
=
= 4A, f


PWM
1 (
–
3 )
s
= V
1
= 300kHz,
T
-------------- -
R
= 10kΩ.
o
= 0.15Ω
IN
1
C
1
/11,
c
o
is
has unity
(EQ. 26)
(EQ. 27)
(EQ. 28)
ISL6253
PCB Layout Considerations
Power and Signal Layer Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. For example, layer
arrangement on a 4 layer board is shown below:
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT
traces can be short.
Place the components in such a way that the area under the
IC has fewer noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
SIGNAL GROUND AND POWER GROUND CONNECTION
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
GND AND VDD PIN
At least one high quality ceramic decoupling cap should be
used to cross the GND and VDD pins. The decoupling cap
can be put close to the IC.
LGATE PIN
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
PGND PIN
The PGND pin should be laid out to the negative side of the
relevant output cap with separate traces. The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET.
Layer 1: Small signal external components
Layer 2: Signal Ground
Layer 3: Power Ground
Layer 4: Bottom Layer: Power MOSFET, Inductors and
other Power traces