NCP1207DR2 ON Semiconductor, NCP1207DR2 Datasheet - Page 11

• Manufacturer Part Number: NCP1207DR2
• Description: IC CTRLR PWM CM OVP OCP HV 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1207DR2

• Output Isolation: Isolated
• Voltage - Input: 10.6 ~ 16 V
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: NCP1207DR2OSTR

COMPARATOR
Demagnetization Detection
activity on the auxiliary winding. This voltage features a
FLYBACK polarity. The typical detection level is fixed at
50 mV as exemplified by Figure 21.
to the driver going−low transition. This prevents the
switching frequency to exceed (1 / (T
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
specific component arrangement as detailed by Figure 22. In
this picture, the zener diodes network protect the IC against
any potential ESD discharge that could appear on the pins.
The first ESD diode connected to the pad, exhibits a parasitic
capacitance. When this parasitic capacitance (10 pF
typically) is combined with R
and the possibility to switch right in the drain−source wave
exists. This guarantees QR operation with all the associated
benefits (low EMI, no turn−on losses etc.). R
calculated to limit the maximum current flowing through
pin 1 to less than +3 mA/−2 mA. If during turn−on, the
auxiliary winding delivers 30 V (at the highest line level),
then the minimum R
(30 V + 0.7 V) / 2 mA = 14.6 kW.
This value will be further increased to introduce a restart
delay and also a slight filtering in case of high leakage
energy.
power.
TO INTERNAL
R
−1.0
The core reset detection is done by monitoring the voltage
esd
An internal timer prevents any restart within 8.0 ms further
The 1207 demagnetization detection pad features a
Figure 23 portrays a typical V
Figure 21. Core reset detection is done through a
7.0
5.0
3.0
1.0
+ R
dedicated auxiliary winding monitoring
int
R
Figure 22. Internal Pad Implementation
RESTARTS
int
POSSIBLE
= 28 k
dem
2
ESD2
0 V
R
value is defined by:
esd
dem
DS
, a restart delay is created
1
ESD1
shot at nominal output
ON
1
4
+ 8.0 ms)) but also
5
R
dem
50 mV
dem
should be
http://onsemi.com
4
3
Aux
NCP1207
11
Overvoltage Protection
voltage 4.5 ms after the turn−off sequence. This delay
guarantees a clean plateau, providing that the leakage
inductance ringing has been fully damped. If this would not
be the case, the designer should install a small RC damper
across the transformer primary inductance connections.
Figure 24 shows where the sampling occurs on the auxiliary
winding.
enters a latchoff phase and stops all switching operations.
The controller stays fully latched in this position and the
DSS is still active, keeping the V
in normal operations. This state lasts until the V
down 4 V, e.g. when the user unplugs the power supply from
the mains outlet.
reference level and pin 1 is routed via a divide by 1.44
network. As a result, when V
comparator is triggered. The threshold can thus be adjusted
by either modifying the power winding to auxiliary winding
turn ratios to match this 7.2 V level, or insert a resistor from
pin1 to ground to cope with your design requirement.
The overvoltage protection works by sampling the plateau
When an OVP condition has been detected, the NCP1207
By default, the OVP comparator is biased to a 5 V
400
300
200
100
8.0
6.0
4.0
2.0
Figure 24. A voltage sample is taken 4.5 ms after
0
0
Figure 23. The NCP1207 Operates in
Borderline / Critical Operation
4.5 ms
the turn−off sequence
pin1
CC
reaches 7.2 V, the OVP
between 5.3 V/12 V as
SAMPLING HERE
CC
is cycled