NCP1217P100G ON Semiconductor, NCP1217P100G Datasheet - Page 13
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NCP1217P100G
Manufacturer Part Number
NCP1217P100G
Description
IC CTRLR PWM CM OVP HV 8DIP
Manufacturer
ON Semiconductor
Datasheet
1.NCP1217P100G.pdf
(19 pages)
Specifications of NCP1217P100G
Output Isolation
Isolated
Frequency Range
90 ~ 110kHz
Voltage - Input
10 ~ 16 V
Operating Temperature
0°C ~ 150°C
Package / Case
8-DIP (0.300", 7.62mm), 7 Leads
Number Of Outputs
1
Duty Cycle (max)
74 % (Typ)
Output Current
500 mA
Mounting Style
Through Hole
Switching Frequency
100 KHz (Typ)
Operating Supply Voltage
16 V
Maximum Operating Temperature
+ 150 C
Fall Time
20 ns
Rise Time
60 ns
Synchronous Pin
No
Topology
Flyback
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NCP1217P100GOS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NCP1217P100G
Manufacturer:
SUPERTEX
Quantity:
16 700
level, the default one or lower. As soon as some external
signal pulls this Adj pin level above 3.1 V typical, the output
pulses are permanently disabled. Care must be taken to limit
the injected current into pin 1 to less than 2.0 mA, e.g.
through a series resistor of 5.6 k with a 10 V V
startup switch is activated every time V
maintains a V
5.6 V and 12.8 V. Reset occurs when V
e.g. when the user cycle the SMPS down. Figure 25
illustrates the operation. Adding a zener diode from Q1 base
to ground makes a cheap OVP, protecting the supply from
any lethal open- -loop operation. If a thermistor (NTC) is
added in parallel with the Zener- -diode, overtemperature
protection is also ensured.
In normal operation, the Adj pin level is kept at a fixed
Figure 24. When Vadj is Pulled Above 3.1 V, NCP1217 Permanently Latches- -Off the Output Pulses
CC
voltage ramping up and down between
VCC
VCC
VCC
ON
latch
min
= 12.8 V
= 7.6 V
= 5.6 V
V
Drv
Adj
CC
CC
CC
reaches 5.6 V and
falls below 5.6 V,
adj level
Fault brings adj above latching level
Default
Driver
Pulses
CC
http://onsemi.com
. The
Reset level
13
The startup current source keeps the
device latched until reset occurs.
Latched--off
Nonlatching Shutdown
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj Pin 1 level, the
output pulses are disabled as long as FB is pulled below
Pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 26 depicts the application example.
T
In some cases, it might be desirable to shut off the part
Figure 25. A Thermistor and a Zener Diode Offer
Both OVP and Overtemperature Latched- -Off
OVP
Protection
1
2
3
4
Vaux
Time
Time
Time
8
7
6
5
<16 V
CV
CC
Laux