NCP1203P60G ON Semiconductor, NCP1203P60G Datasheet - Page 11

• Manufacturer Part Number: NCP1203P60G
• Description: IC CTRLR PWM CM UVLO HV 8DIP
• Manufacturer: ON Semiconductor

Specifications of NCP1203P60G

• Output Isolation: Isolated
• Frequency Range: 57 ~ 73kHz
• Voltage - Input: 8.4 ~ 16 V
• Voltage - Output: 500V
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Outputs: 1
• Duty Cycle (max): 80 % (Typ)
• Output Current: 250 mA
• Mounting Style: Through Hole
• Switching Frequency: 65 KHz (Typ)
• Operating Supply Voltage: 16 V
• Maximum Operating Temperature: 125 C
• Fall Time: 28 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 67 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCP1203P60GOS

Full Latching Shutdown
when an abnormal situation is detected (overtemperature or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
current flowing through Rhold should be small enough to let
the V
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolars can be MMBT2222
and MMBT2907 for the discrete latch. The MMBT3946
features two bipolars NPN+PNP in the same package and
could also be used.
Protecting the Controller Against Negative Spikes
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
path is offered between V
Other applications require a full latching shutdown, e.g.
Rhold ensures that the SCR stays on when fired. The bias
As with any controller built upon a CMOS technology, it
CC
ramp up (12.8 V) and down (4.9 V) when the SCR
0.1 mF
Figure 20. Two Bipolars Ensure a Total Latch- -Off of the SMPS in Presence of an OVP
Figure 19. Another Way of Shutting Down the IC without a Definitive Latch- -Off State
OVP
CC
and GND. If the current sense
10 k
ON/OFF
10 k
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When the V
the NPN biases the PNP and fires the equivalent SCR,
permanently bringing down the FB pin. The switching
pulses are disabled until the user unplugs the power supply.
pin is often the seat of such spurious signals, the
high- -voltage pin can also be the source of problems in
certain circumstances. During the turn- -off sequence, e.g.
when the user un- -plugs the power supply, the controller is
still fed by its V
MOSFET ON and OFF with a peak current limited by
Rsense. Unfortunately, if the quality coefficient Q of the
resonating network formed by Lp and Cbulk is low (e.g. the
MOSFET Rdson + Rsense are small), conditions are met to
make the circuit resonate and thus negatively bias the
controller. Since we are talking about ms pulses, the amount
of injected charge (Q = I x t) immediately latches the
controller which brutally discharges its V
V
damages the controller. Figure 21 depicts a typical negative
shot occurring on the HV pin where the brutal V
testifies for latchup.
CC
capacitor is of sufficient value, its stored energy
Q1
1
2
3
4
CC
NCP1203
Rhold
12 k
level exceeds the zener breakdown voltage,
CC
1
2
3
4
capacitor and keeps activating the
8
7
6
5
CV
8
7
6
5
CC
CC
LAux
capacitor. If this
CC
discharge