DS1216B Maxim Integrated Products, DS1216B Datasheet - Page 4

• Manufacturer Part Number: DS1216B
• Description: IC SMARTWATCH RAM 16K/64K 28SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS1216B

• Controller Type: Smartwatch RAM
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm) Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

comparison register and awaits the next write cycle. If a match is not found, the pointe
and all subsequent write cycles are ignored. If a read cycle occurs at any time during p
the present sequence is aborted and the comparison register pointer is reset. Pattern rec
for 64 write cycles as described above until all the bits in the comparison register have been m
bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch i
transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Sm
to either receive or transmit data on DQ0, depending on the level of the OE pin or the
other locations outside the memory block can be interleaved with CE cycles witho
pattern recognition sequence or data transfer sequ
PATTERN MATCH—ROM
Communication with the SmartWatch is established by pattern recognition of
that must be matched by executing 64 consecutive write cycles, placing address bi
proper data on address bit A0. The 64 write cycles are used only to gain access to the
to executing the first of 64 write cycles, a read cycle should be executed by holding
cycle will reset the comparison register poi
starts with the
the 64-bit comparison register. If a match is found, the pointer increments to the n
comparison register and awaits the next write cycle. If a match is not found, the pointe
and all subsequent write cycles are ignored. If a read cycle occurs at any time during p
the present sequence is aborted and the comparison register pointer is reset. Pattern rec
for a total of 64 write cycles as described above, until all the bits in the comparison
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits,
enabled and data transfer to or from the timekeeping registers can proceed. The next 6
the SmartWatch to either receive data on data in (A0) or transmit data on data out (D
the leve
After power-up, the controller could be in the 64-bit clock register read/write sequence (from
incomplete access prior to power-down). Therefore, it is recommended that a 64-bit
upon power-up to prevent accidental writes to the clock, and to prevent reading clock d
the RAM would otherwise be expected.
l of /WRITE READ (A2).
first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of
nter within the SmartWatch, ensuring the pattern recognition
ence to the SmartWatch.
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DS1216 SmartWatch RAM/SmartWatch ROM
a serial bit stream of 64 bits
ext location of the
the SmartWatch is
t A2 low with the
s enabled and data
4 cycles will cause
Q0), depending on
r does not advance
ut interrupting the
SmartWatch. Prior
r does not advance
A2 high. The read
read be performed
ognition continues
ognition continues
register have been
ata when access to
WE pin. Cycles to
attern recognition,
attern recognition,
atched (this
artWatch
an