AT17C002-10JC Atmel, AT17C002-10JC Datasheet - Page 6
![IC SRL CONFIG EEPROM 2M 20PLCC](/photos/6/80/68044/453-20-plcc_sml.jpg)
AT17C002-10JC
Manufacturer Part Number
AT17C002-10JC
Description
IC SRL CONFIG EEPROM 2M 20PLCC
Manufacturer
Atmel
Datasheet
1.AT17C002-10CI.pdf
(19 pages)
Specifications of AT17C002-10JC
Programmable Type
Serial EEPROM
Memory Size
2Mb
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Package / Case
20-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Example Circuits
Figure 1. AT17 Series Device for Programming PSLI Devices
Notes:
The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by
the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration
before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator’s inter-
nal address pointer so that the reconfiguration starts at the beginning.
Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications
Notes:
6
RESET
PROGRAM
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
1. Reset polarity must be set to active Low.
1. Reset polarity must be set to active Low.
AT17C/LV002
GND
GND
AT40K/AT40KAL/AT94K
RESET
M2
M1
M0
PROGRAM
M2
M1
M0
XILINX FPGA
DATA0
CCLK
DONE
CON
INIT
CCLK
INIT
DIN
(3)
V
CC
4.7 k
9
DATA
CLK
CE
RESET/OE
DATA
CLK
CE
RESET/OE
AT17 Series Device
AT17 Series Device
(1)
(1)
READY
READY
SER_EN
SER_EN
(2)
(2)
2281D–12/01
V
V
CC
CC