EPC1PI8N Altera, EPC1PI8N Datasheet - Page 8
![IC CONFIG DEVICE 1MBIT 8-DIP](/photos/7/31/73168/544-8-dip_sml.jpg)
EPC1PI8N
Manufacturer Part Number
EPC1PI8N
Description
IC CONFIG DEVICE 1MBIT 8-DIP
Manufacturer
Altera
Series
EPCr
Datasheet
1.EPC1PC8.pdf
(26 pages)
Specifications of EPC1PI8N
Programmable Type
OTP
Memory Size
1Mb
Voltage - Supply
3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
For Use With
PLMJ1213 - PROGRAMMER ADAPTER 20 PIN J-LEAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1375-5
EPC1PI8N
EPC1PI8N
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
EPC1PI8N
Manufacturer:
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4–8 Chapter 4: Configuration Devices for SRAM-Based LUT Devices Data Sheet
Figure 4–3. Altera FPGA Configured Using Two EPC1 or EPC2 Configuration Devices
Notes to
(1) For specific details about configuration interface connections refer to the appropriate FPGA family chapter in the
(2) The nINIT_CONF pin (available on EPC2 devices) has an internal pull-up resistor that is always active. This means an external pull-up resistor
(3) EPC2 devices have internal programmable pull-up resistors on OE and nCS. If internal pull-up resistors are used, external pull-up resistors should
Configuration Handbook (Complete Two-Volume Set)
is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If
nINIT_CONF is not used or not available, nCONFIG must be pulled to V
not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
Figure
n
4–3:
MSEL
When the first device in a configuration device chain is powered-up or reset, its nCS
pin is driven low because it is connected to the CONF_DONE of the FPGA. Because both
OE and nCS are low, the first device in the chain will recognize it is the master device
and will control configuration. Since the slave devices’ nCS pin is fed by the previous
devices’ nCASC pin, its nCS pin will be high upon power-up and reset. In the slave
configuration devices, the DATA output is tri-stated and DCLK is an input. During
configuration, the master device supplies the clock through DCLK to the FPGA and to
any slave configuration devices. The master EPC1 or EPC2 device also provides the
first stream of data to the FPGA during multi-device configuration. After the master
EPC1 or EPC2 device finishes sending configuration data, it tri-states its DATA pin to
avoid contention with other configuration devices. The master EPC1 or EPC2 device
will also drive its nCASC pin low, which pulls the nCS pin of the next device low. This
action signals the slave EPC1 or EPC2 device to start sending configuration data to the
FPGAs.
The master EPC1 or EPC2 device clocks all slave configuration devices until
configuration is complete. When all configuration data is transferred and the nCS pin
on the master EPC1 or EPC2 device is driven high by the FPGA’s CONF_DONE pin, the
master EPC1 or EPC2 device then goes into zero-power (idle) state. The master EPC2
device drives DATA high and DCLK low, while the EPC1 and EPC1441 device tri-state
DATA and drive DCLK low.
If nCS on the master EPC1 or EPC2 device is driven high before all configuration data
is transferred, the master EPC1 or EPC2 device drives its OE signal low, which in turn
drives the FPGA’s nSTATUS pin low, indicating a configuration error. Additionally, if
the configuration device sends is generated its data and detects that CONF_DONE has
not gone high, it recognizes that the FPGA has not configured successfully. EPC1 and
EPC2 devices wait for 16 DCLK cycles after the last configuration bit was sent for
CONF_DONE to reach a high state. In this case, the configuration device pulls its OE pin
FPGA
CONF_DONE
nSTATUS
nCONFIG
DATA0
DCLK
nCEO
nCE
GND
N.C.
V
CC
(3)
V
CC
(2)
V
CC
(3)
CC
either directly or through a resistor.
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
Configuration
Master
Device
nCASC
(Note 1)
© December 2009
DCLK
DATA
nCS
OE
Configuration
Configuration
Device
Slave
nCASC
Device Configuration
Altera Corporation
Handbook.
N.C.