AT17N256-10PC Atmel, AT17N256-10PC Datasheet - Page 5

• Manufacturer Part Number: AT17N256-10PC
• Description: IC FPGA 256K CONFIG MEM 8DIP
• Manufacturer: Atmel

Specifications of AT17N256-10PC

• Programmable Type: Serial EEPROM
• Memory Size: 256Kb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• For Use With: ATDH2225 - CABLE ISP FOR AT17ATDH2200E - CONFIGURATOR PROGRAM BOARD KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Description
DATA
CLK
RESET/OE
CE
GND
VCC(SER_EN)
V
NC
DC
3020C–CNFG–08/07
CC
VCC(SER_EN)
RESET/OE
Name
DATA
GND
CLK
V
DC
DC
CE
CC
I/O
I/O
O
O
I
I
I
I
SOIC
DIP/
8
1
2
3
4
5
6
–
7
8
AT17N256
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
Ground pin. A 0.2 µF decoupling capacitor between V
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
3.3V (±10%) Commercial and Industrial power supply pin.
NC pins are No Connect pins, which are not internally bonded out to the die.
DC pins are No Connect pins internally connected to the die. It is not recommended to
connect these pins to any external signal.
SOIC
20
10
11
13
18
20
1
3
8
–
DIP
8
1
2
3
4
5
6
–
7
8
AT17N512/
AT17N010
CC
.
AT17N256/512/010/002/040
SOIC
20
10
11
13
18
20
1
3
8
–
SOIC
20
10
11
13
18
20
1
3
8
–
CC
AT17N002
and GND is recommended.
TQFP
44
40
43
13
15
18
21
23
35
38
AT17N040
TQFP
44
40
43
13
15
18
21
23
35
38
5