EPC2LC20 Altera, EPC2LC20 Datasheet - Page 12

• Manufacturer Part Number: EPC2LC20
• Description: IC CONFIG DEVICE 1.6MBIT 20-PLCC
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC2LC20

• Programmable Type: In System Programmable
• Memory Size: 1.6Mb
• Voltage - Supply: 3 V ~ 3.6 V, 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-PLCC
• Memory Type: Flash
• Supply Voltage Range: 4.75V To 5.25V
• Memory Case Style: LCC
• No. Of Pins: 20
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LCC
• Rohs Compliant: No
• For Use With: PLMJ1213 - PROGRAMMER ADAPTER 20 PIN J-LEAD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1233-5

4–12 Chapter 4: Configuration Devices for SRAM-Based LUT Devices Data Sheet
Programming and Configuration File Support
Configuration Handbook (Complete Two-Volume Set)
f
1
The Quartus II and MAX+PLUS II softwares provide programming support for Altera
configuration devices. During compilation, the Quartus II and MAX+PLUS II
softwares automatically generates a .pof, which can be used to program the
configuration devices. In a multi-device project, the software can combine the
programming files for multiple ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,
Cyclone II, FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
into one or more configuration devices. The software allows you to select the
appropriate configuration device to most efficiently store the data for each FPGA.
All Altera configuration devices are programmable using Altera programming
hardware in conjunction with the Quartus II or MAX+PLUS II software. In addition,
many third part programmers offer programming hardware that supports Altera
configuration devices.
An EPC2 device can be programmed with a .pof generated for an EPC1 or EPC1441
device. An EPC1 device can be programmed using a .pof generated for an EPC1441
device.
EPC2 configuration devices can be programmed in-system through its
industry-standard 4-pin JTAG interface. ISP capability in the EPC2 devices provides
ease in prototyping and FPGA functionality. When programming multiple EPC2
devices in a JTAG chain, the Quartus II and MAX+PLUS II softwares and other
programming methods employ concurrent programming to simultaneously program
multiple devices and reduce programming time. EPC2 devices can be programmed
and erased up to 100 times.
After programming an EPC2 device in-system, FPGA configuration can be initiated
by the EPC2 INIT_CONF JTAG instruction. Refer to
For more information about programming and configuration support, refer to the
following documents:
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You can also program configuration devices using the Quartus II or MAX+PLUS II
software with the APU, and the appropriate configuration device programming
adapter.
Altera Programming Hardware Data Sheet
USB-Blaster Download Cable User Guide
MasterBlaster Serial/USB Communications Cable User Guide
ByteBlaster II Download Cable User Guide
ByteBlasterMV Download Cable User Guide
BitBlaster Serial Download Cable Data Sheet
Table 4–6 on page
Programming and Configuration File Support
© December 2009
4–14.
Altera Corporation