CAT93C66XI ON Semiconductor, CAT93C66XI Datasheet - Page 6

• Manufacturer Part Number: CAT93C66XI
• Description: IC EEPROM 4KBIT 2MHZ 8SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT93C66XI

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 4Kb
• Interface Type: Serial (Microwire)
• Organization: 512x8/256x16
• Frequency (max): 500KHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC EIAJ
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read
(clocked into the DI pin), the DO pin of the CAT93C66 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
Upon receiving a READ command and an address
For the CAT93C66, after the initial data word has been
DO
SK
CS
DI
DO
SK
CS
DI
1
t
PD0
CSS
1
or t
0
PD1
HIGH−Z
).
A
VALID
N
t
A
DIS
N−1
Figure 2. Synchronous Data Timing
Figure 3. READ Instruction Timing
t
SKHI
t
Dummy 0
PD0
http://onsemi.com
A
t
0
DIS
t
SKLOW
6
D
or
D
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
Erase/Write Enable and Disable
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C66 write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status. The
EWEN and EWDS instructions timing is shown in Figure 4.
15 . . .
7 . . .
The CAT93C66 powers up in the write disable state. Any
VALID
D
D
0
0
Address +
D
or
D
15 . . .
7 . . .
Don’t Care
t
t
DIH
PD0
D
DATA VALID
D
0
0
, t
1
PD1
Address +
D
or
D
15 . . .
7 . . .
t
D
CSH
D
0
0
2
Address + n
D
or
D
15 . . .
7 . . .
t
CSMIN