HYB25D256160CE-5 Qimonda, HYB25D256160CE-5 Datasheet
HYB25D256160CE-5
Specifications of HYB25D256160CE-5
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HYB25D256160CE-5 Summary of contents
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... We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) ...
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Overview This chapter lists all main features of the product family HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) and the ordering information. 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with ...
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... DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 256 Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK ...
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... HYB25D256160CE–5A ×4 HYB25D256400CE–5 ×8 HYB25D256800CE–5 ×16 HYB25D256160CE–5 ×8 HYB25D256800CE–6 ×8 HYB25D256800CEL–6 ×16 HYB25D256160CE–6 ×16 HYB25D256160CEL–6 ×4 HYB25D256400CE–7 ×4 HYB25D256400CF–5 ×8 HYB25D256800CF–5 ×16 HYB25D256160CF–5 ×4 HYB25D256400CF–6 ×8 HYB25D256800CF–6 ×16 HYB25D256160CF– ...
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... HYI25D256800CC–5 ×16 HYI25D256160CC–5 ×8 HYI25D256800CC–6 ×16 HYI25D256160CC–6 1) HYB and HYI: designator for memory components; V 25D: DDR SDRAMs at = 2.5 V; DDQ 256: 256-Mbit density; 400/800/160: product variations ×4, ×8 and ×16; C: die revision C; L: low power (available on request); ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in column are explained in Table 5 and Table 6 TSOP package in Figure 2. Ball#/Pin# Name Pin Type Clock Signals G2 G3, ...
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Ball#/Pin# Name Pin Type Data Signals ×4 Organization B7, 5 DQ0 I/O D7, 11 DQ1 I/O D3, 56 DQ2 I/O B3, 62 DQ3 I/O Data Strobe ×4 Organisation E3, 51 DQS I/O Data Mask ×4 Organization F3 ...
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Ball#/Pin# Name Pin Type Data Strobe ×16 organization E3, 51 UDQS I/O E7, 16 LDQS I/O Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1 REF V A9, B2, C8, D2, ...
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Ball#/Pin# Name Pin Type F9, 14, 17, 19 25,43, 50, 53 Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is ...
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Pin Configuration P-TFBGA-60 Top View, see the balls throught the package Rev. 2.4, 2007-07 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T]( ...
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Rev. 2.4, 2007-07 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM Pin Configuration P-TSOPII-66-1 12 Internet Data Sheet FIGURE 2 ...
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Functional Description 1) Field Bits Type Description BL [2:0] W Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001 2 B 010 4 B 011 8 B ...
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Burst Length Starting Column Address ...
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Field Bits Type Description DLL 0 W DLL Status Drive Strength MODE [12:2] W Operating Mode Note: All other bit combinations are RESERVED. 00000000000 write ...
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Name (Function) Write Enable Write Inhibit 1) Used to mask write data; provided coincident with the corresponding data. Current State CKE n-1 CKEn Previous Cycle Current Cycle Self Refresh L L Self Refresh L H Power Down L L Power ...
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Current State CS RAS CAS WE Any Idle Row Active ...
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Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any Idle Row Activating Active ...
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Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt ...
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Electrical Characteristics This chapter lists the electrical characteristics. 4.1 Operating Conditions This chapter contains the operating conditions tables. Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply ...
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Parameter Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS These values are not subject to production ...
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Parameter Symbol V Device Supply Voltage DD V Device Supply Voltage DD V Output Supply Voltage DDQ V Output Supply Voltage DDQ V V Supply Voltage, I/O Supply , SS SSQ Voltage V Input Reference Voltage REF V I/O Termination ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I Specifications and Conditions, and Electrical Characteristics and AC Timing.) DD Notes V 1. All voltages referenced ...
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Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs V = 2.5 V ...
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Parameter Symbol t DQS falling edge hold time from DSH CK (write cycle) t DQS falling edge to CK setup time DSS (write cycle) t Clock Half Period HP t Data-out high-impedance time HZ from CK/CK t Address and control ...
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Parameter Symbol t Internal write to read command WTR delay t Exit self-refresh to non-read XSNR command t Exit self-refresh to read command XSRD 1) 0 °C ≤ T ≤ 70 ° 2.5 V ± 0.2 V, ...
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Parameter DQ output access time from CK/CK CK high-level width Clock cycle time CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access ...
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Parameter Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Auto-refresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write ...
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Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page ...
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Symbol –5 –6 DDR400B DDR333 Typ. Max. Typ DD0 100 70 DD1 95 110 DD2P DD2F DD2Q I ...
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Package Outlines There are two package types used for this product family each in lead-free and lead-containing assembly: • P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package Description Ball Size Recommended Landing Pad Recommended Solder Mask Rev. 2.4, 2007-07 ...
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P(G)-TFBGA-60: Plastic (non-green/green) Thin Fine Ball Grid Array Rev. 2.4, 2007-07 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM Package Outline of P-TFBGA-60-12 (non-green/green) 32 Internet Data Sheet FIGURE 4 ...
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Rev. 2.4, 2007-07 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM Package Outline of P-TSOPII-66-1 (non-green/green) 33 Internet Data Sheet FIGURE 5 ...
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List of Figures Figure 1 Pin Configuration P-TFBGA-60 Top View, see the balls throught the package . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Performance of –5, –6 and – ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...