MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet - Page 69

• Manufacturer Part Number: MD5811-D256-V3Q18-P
• Description: IC MDOC P3 256MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD5811-D256-V3Q18-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 256M (32M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-Bit (Byte) Data Access Mode
When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines
D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even
address accesses to the appropriate byte lane of the flash and RAM.
Host address SA0 must be connected to Mobile DiskOnChip P3 A0, SA1 must be connected to A1, etc.
16-Bit (Word) Data Access Mode
To set Mobile DiskOnChip P3 to work in 16-bit mode, the IF_CFG pin/ball must be connected to VCC.
In 16-bit mode, the Programmable Boot Block is accessed as a true 16-bit device. It responds with
the appropriate data when the CPU issues either an 8-bit or 16-bit read cycle. The flash area is
accessed as a 16/32-bit device, regardless of the interface bus width. This has no affect on the
design of the interface between Mobile DiskOnChip P3 and the host. The TrueFFS driver handles
all issues regarding moving data in and out of Mobile DiskOnChip P3.
See Table 6 for A0 and IF_CFG settings for various functionalities with 8/16-bit data access.
32-Bit (Double Word) Data Access Mode
In a 32-bit bus system that cannot execute byte or word aligned accesses, the system address lines
SA0 and SA1 are always 0. Consecutive double words (32-bit words) are differentiated by SA2
toggling. Therefore, in 32-bit systems that support only 32-bit data access cycles, Mobile
DiskOnChip P3 signal A0 is connected to VSS and A1 is connected to the first system address bit
that toggles; i.e., SA2.
66
Note: The prefix “S” indicates system host address lines
SA13
A12
SA12
A11
Figure 22: Address Shift Configuration for 32-Bit Data Access Mode
A0
0
0
1
1
SA11
A10
Table 6: Active Data Bus Lines in 8/16-Bit Configuration
IF_CFG
SA10
A9
1
0
0
1
SA9
A8
16-bit access through both buses
8-bit access to even bytes through low 8-bit bus
8-bit access to odd bytes through low 8-bit bus
Illegal
Mobile DiskOnChip P3
SA8
Data Sheet, Rev. 0.3
A7
System
SA7
Host
A6
SA6
Functionality
A5
SA5
A4
SA4
A3
SA3
A2
SA2
A1
SA1
A0
Mobile DiskOnChip P3
SA0
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