DS1251YP-70 Maxim Integrated Products, DS1251YP-70 Datasheet - Page 18
![IC NVSRAM 4MBIT 70NS 34PCM](/photos/6/58/65856/406-34-pcm_sml.jpg)
DS1251YP-70
Manufacturer Part Number
DS1251YP-70
Description
IC NVSRAM 4MBIT 70NS 34PCM
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1251Y-70.pdf
(21 pages)
Specifications of DS1251YP-70
Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
4M (512K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
34-PowerCap™ Module
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) WE is high for a read cycle.
2) OE = V
3) t
4) t
5) These parameters are sampled with a 50pF load and are not 100% tested.
6) If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle
7) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
8) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
9) The expected t
10) t
11) Voltages are referenced to ground.
12) RST (Pin 1) has an internal pullup resistor.
13) Real-time clock modules can be successfully processed through conventional wave-soldering
In addition, for the PowerCap:
1) Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
2) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three
low to the earlier of CE or WE going high.
1, the output buffers remain in a high-impedance state during this period.
buffers remain in a high-impedance state during this period.
the output buffers remain in a high impedance state during this period.
running.
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable, provided that
ultrasonic vibration is not used.
reflow oriented with the label side up (“live-bug”).
seconds.
To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part,
WP
DH
WR
, t
apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove
solder.
is specified as the logical AND of CE and WE. t
is a function of the latter occurring edge of WE or CE.
DS
IH
are measured from the earlier of CE or WE going high.
or V
IL
DR
. If OE = V
is defined as cumulative time in the absence of V
IH
during write cycle, the output buffers remain in a high-impedance state.
18 of 21
WP
is measured from the latter of CE or WE going
CC
with the clock oscillator