R1LP0408CSB-5SC#S0 Renesas Electronics America, R1LP0408CSB-5SC#S0 Datasheet - Page 10

• Manufacturer Part Number: R1LP0408CSB-5SC#S0
• Description: IC SRAM 4MBIT 55NS 32TSOP
• Manufacturer: Renesas Electronics America

Specifications of R1LP0408CSB-5SC#S0

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 4M (512K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 32-TSOP II
• Density: 4Mb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 19b
• Package Type: TSOP-II
• Operating Temp Range: -20C to 70C
• Number Of Ports: 1
• Supply Current: 3mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: R1LP0408CSB5SC#S0

R1LP0408C-C Series
Write Cycle
Parameter
Write cycle time
Chip selection to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time
Write to output in high-Z
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in high-Z
Notes: 1. t
Rev.2.00, May.26.2004, page 8 of 12
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
4. t
5. t
6. t
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
12. In the write cycle with OE# low fixed, t
and are not referred to output voltage levels.
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. t
to the outputs must not be applied.
transition, the output remain in a high impedance state.
the opposite phase to the outputs must not be applied to them.
data bus contention. t
HZ
CW
AS
WR
, t
is measured from the address valid to the beginning of write.
is measured from CS# going low to the end of write.
is measured from the earlier of WE# or CS# going high to the end of write cycle.
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit conditions
WP
≥ t
WP
DW
t
t
t
t
t
t
t
t
t
t
Symbol
t
WC
CW
AS
AW
WP
WR
WHZ
DW
DH
OW
OHZ
is measured from the beginning of write to the end of write.
min + t
WP
) of a low CS# and a low WE#. A write begins at the later
WP
WHZ
R1LP0408C-C
-5SC
Min
55
50
0
50
40
0
0
25
0
5
0
must satisfy the following equation to avoid a problem of
max
Max






20



20
-7LC
Min
70
60
0
60
50
0
0
30
0
5
0
Max






25



25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4
5
3, 12
6
1, 2, 7
2
1, 2, 7