STK14C88-NF45 Cypress Semiconductor Corp, STK14C88-NF45 Datasheet - Page 12
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STK14C88-NF45
Manufacturer Part Number
STK14C88-NF45
Description
IC NVSRAM 256KBIT 45NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Specifications of STK14C88-NF45
Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
256K (32K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-SOIC (7.5mm Width)
Word Size
8b
Organization
32Kx8
Density
256Kb
Interface Type
Parallel
Access Time (max)
45ns
Operating Supply Voltage (typ)
5V
Package Type
SOIC
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
0C to 70C
Pin Count
32
Mounting
Surface Mount
Supply Current
70mA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STK14C88-NF45
Manufacturer:
SIMTER
Quantity:
20 000
Company:
Part Number:
STK14C88-NF45I
Manufacturer:
SIMTEK
Quantity:
5 947
Part Number:
STK14C88-NF45I
Manufacturer:
SIMTEK
Quantity:
20 000
Company:
Part Number:
STK14C88-NF45ITR
Manufacturer:
SIMTEK
Quantity:
7 145
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
■
■
Preventing STORES
The STORE function can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a V
2.2V, beause it must overpower the internal pull down device that
drives HSB low for 20 ms at the onset of a STORE. When the
STK14C88 is connected for AutoStore operation (system V
connected to V
crosses V
pull HSB low; if HSB does not actually get below V
stops trying to pull HSB low and abort the STORE attempt.
Hardware Protect
The STK14C88 offers hardware protection against inadvertent
STORE operation and SRAM writes during low voltage condi-
tions. When V
operations and SRAM writes are inhibited.
AutoStore can be completely disabled by tying V
and applying + 5V to V
this mode STOREs are only initiated by explicit request using
either the software sequence or the HSB pin.
Document Number: 001-52038 Rev. *B
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The
end product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (such as autostore enabled). While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on).
The V
and a maximum value size. Best practice is to meet this
requirement and not exceed the max V
nvSRAM internal algorithm calculates V
on this max V
V
time should discuss their V
understand any impact on the V
a t
CAP
RECALL
CAP
value to make sure there is extra store charge and store
SWITCH
value specified in this data sheet includes a minimum
period.
CAP
CAP
CC
on the way down, the STK14C88 attempts to
and a 68 uF capacitor on V
< V
value. Customers who want to use a larger
CAP
SWITCH
. This is the AutoStore Inhibit mode; in
CAP
, all externally initiated STORE
size selection with Cypress to
CAP
voltage level at the end of
CAP
CAP
value because the
charge time based
CAP
CC
OH
IL
) and V
of at least
to ground
, the part
CC
CC
Low Average Active Power
The STK14C88 draws significantly less current when it is cycled
at times longer than 50 ns.
between I
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, V
chip enable).
cycles. If the chip enable duty cycle is less than 100%, only
standby current is drawn when the chip is disabled. The overall
average current drawn by the STK14C88 depends on the
following items:
■
■
■
■
■
■
■
Figure 13. Icc (max) Reads
Figure 14. Icc (max) Writes
CMOS vs. TTL input levels
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of reads to writes
The operating temperature
The V
I/O loading.
CC
CC
level
100
100
80
60
40
20
80
60
40
20
0
0
Figure 14
and read cycle time. Worst case current
50
50
shows the same relationship for write
Cycle Time (ns)
Cycle Time (ns)
100
100
Figure 13
CC
150
150
= 5.5V, 100% duty cycle on
TTL
TTL
CMOS
CMOS
shows the relationship
200
200
STK14C88
Page 12 of 19
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