STK14C88-3NF45 Cypress Semiconductor Corp, STK14C88-3NF45 Datasheet - Page 4

• Manufacturer Part Number: STK14C88-3NF45
• Description: IC NVSRAM 256KBIT 45NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK14C88-3NF45

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOIC (7.5mm Width)
• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 42mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document Number: 001-50592 Rev. *A
Device Operation
The STK14C88-3 nvSRAM is made up of two functional
components paired in the same physical cell. These are an
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation) or from the nonvolatile cell to SRAM (the
RECALL operation). This unique architecture enables the
storage and recall of all cells in parallel. During the STORE and
RECALL operations, SRAM READ and WRITE operations are
inhibited. The STK14C88-3 supports unlimited reads and
writes similar to a typical SRAM. In addition, it provides
unlimited RECALL operations from the nonvolatile cells and
up to one million STORE operations.
SRAM Read
The STK14C88-3 performs a READ cycle whenever CE and
OE are LOW while WE and HSB are HIGH. The address
specified on pins A
accessed. When the READ is initiated by an address
transition, the outputs are valid after a delay of t
cycle 1). If the READ is initiated by CE or OE, the outputs are
valid at t
data outputs repeatedly respond to address changes within
the t
control input pins, and remains valid until another address
change or until CE or OE is brought HIGH, or WE or HSB is
brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW
and HSB is HIGH. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes HIGH at the end of the cycle. The data on the
common I/O pins DQ
valid t
the end of an CE controlled WRITE. Keep OE HIGH during the
entire WRITE cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers t
AutoStore Operation
The STK14C88-3 can be powered in one of three storage
operations:
During normal operation, the device draws current from V
to charge a capacitor connected to the V
charge is used by the chip to perform a single STORE
operation. If the voltage on the V
the part automatically disconnects the V
STORE operation is initiated with power provided by the V
capacitor.
AA
SD
access time without the need for transitions on any
ACE
HZWE
, before the end of a WE controlled WRITE or before
or at t
after WE goes LOW.
DOE
0–14
0–7
, whichever is later (READ cycle 2). The
are written into the memory if it has
determines the 32,768 data bytes
CC
pin drops below V
CAP
CAP
pin from V
pin. This stored
AA
SWITCH
(READ
CC
CAP
. A
CC
,
Figure 2
(V
capacitor having a capacity of between 68 uF and 220 uF
(+20%) rated at 4.7V should be provided.
Figure 2. AutoStore Mode
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. An optional pull-up resistor is shown connected
to
if an AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc
reaches V
between V
excess of current between V
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then V
is tied to ground and +3.3V is applied to V
page 5). This is the AutoStore Inhibit mode, where the
AutoStore function is disabled. If the STK14C88-3 is operated
in this configuration, references to V
throughout this data sheet. In this mode, STORE operations
are triggered through software control. It is not permissible to
change between these options “On the fly”.
CAP
HSB.
) for automatic store operation. A charge storage
The HSB signal is monitored by the system to detect
shows the proper connection of the storage capacitor
SWITCH
CC
and the system supply to avoid momentary
, then a 1 ohm resistor should be connected
CC
and V
CC
CAP
are changed to V
.
STK14C88-3
CAP
(Figure 3
Page 4 of 17
CAP
CC
on
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