W25Q16VSSIG Winbond Electronics, W25Q16VSSIG Datasheet
W25Q16VSSIG
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W25Q16VSSIG Summary of contents
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... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: October 7, 2009 - 1 - W25Q16V Revision E ...
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... Top/Bottom Block Protect (TB) 10.1.5 Sector/Block Protect (SEC) 10.1.6 Status Register Protect (SRP1, SRP0) 10.1.7 Quad Enable (QE) 10.1.8 Status Register Memory Protection 10.2 INSTRUCTIONS 10.2.1 Manufacturer and Device Identification 10.2.2 Instruction Set Table 1 10.2.3 Instruction Set Table 2 (Read Instructions) Table of Contents ...
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Write Enable (06h) 10.2.5 Write Disable (04h) 10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h) 10.2.7 Write Status Register (01h) 10.2.8 Read Data (03h) 10.2.9 Fast Read (0Bh) 10.2.10 Fast Read Dual Output (3Bh) 10.2.11 Fast Read ...
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SOIC 300-mil (Package Code SF) 13. ORDERING INFORMATION 13.1 Valid Part Numbers and Top Side Marking 14. REVISION HISTORY ................................................................................................................ 59 .................................................................... 56 .................................................................................................... 57 .................................................................. W25Q16V ...
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... GENERAL DESCRIPTION The W25Q16 (16M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and 1µ ...
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PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25Q16 Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q16 Pad Assignments, 8-pad WSON (Package Code ZP) 5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM PIN ...
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PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q16 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N/C 7 /CS ...
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... Status Register’s Block Protect (SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2 ...
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BLOCK DIAGRAM Block Segmentation Block Segmentation xxFF00h xxFF00h xxFFFFh xxFFFFh • • Sector 15 (4KB) Sector 15 (4KB) xxF000h xxF000h xxF0FFh xxF0FFh xxEF00h xxEF00h xxEFFFh xxEFFFh • • Sector 14 (4KB) Sector 14 (4KB) xxE000h xxE000h xxE0FFh xxE0FFh xxDF00h ...
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FUNCTIONAL DESCRIPTION 9.1 SPI OPERATIONS 9.1.1 Standard SPI Instructions The W25Q16 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI ...
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... Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the devices write protection features and Quad SPI setting ...
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Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply ...
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Figure 3a. Status Register-1 Figure 3b. Status Register W25Q16V ...
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... Status Register Memory Protection (1) STATUS REGISTER (2) SEC TB BP2 BP1 BP0 Note don’t care 2. When SEC=1, Block Erase (32KB or 64KB) instructions should not issued to Top or Bottom Blocks. W25Q16 (16M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 31 1F0000h - 1FFFFFh 30 and 31 1E0000h - 1FFFFFh ...
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... This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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... A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 FFh dummy dummy dummy dummy dummy dummy (M7-M0) (ID15-ID8) Manufacturer Memory Type - 17 - W25Q16V BYTE 4 BYTE 5 BYTE 6 A7–A0 (D7–D0) (3) A7–A0 (D7–D0, …) A7–A0 A7–A0 A7–A0 (5) dummy (ID7-ID0) ...
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Instruction Set Table 2 (Read Instructions) INSTRUCTION BYTE 1 NAME (CODE) Read Data 03h Fast Read 0Bh Fast Read Dual Output 3Bh Fast Read Dual I/O BBh Fast Read Quad Output 6Bh Fast Read Quad I/O EBh Octal Word ...
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Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip ...
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Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 ...
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... The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0 set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table and description). The Write Status Register instruction also allows the Status Register Protect bits (SRP0, SRP1 set ...
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... DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F eight “dummy” clocks after the 24-bit address as shown in figure 9. The ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins twice the rate of standard SPI devices. The ...
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Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins executed before the device will accept the ...
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Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO and similar to the Fast Read Dual Output (3Bh) instruction but with ...
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Figure 12b. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = Axh) Publication Release Date: October 7, 2009 - 27 - W25Q16V Revision E ...
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Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO clock are required ...
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Figure 13b. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = Axh) Publication Release Date: October 7, 2009 - 29 - W25Q16V Revision E ...
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Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As ...
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Figure 14b. Octal Word Read Quad I/O Instruction Sequence (M7-0 = Axh W25Q16V ...
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... Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data ...
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... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Erase Suspend (75h) The Erase Suspend instruction “75h”, allows the system to interrupt a sector or block erase operation and then read from or program data to, any other sector or block. The Write Status Register instruction (01h) and ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To ...
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Figure 25. Release Power-down / Device ID Instruction Sequence Diagram - 41 - W25Q16V Publication Release Date: October 7, 2009 Revision E ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...
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Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q16 device. The ID number can be used in conjunction with user software methods to help prevent ...
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... The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. For memory type and capacity values refer to Manufacturer and Device Identification table. ...
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Continuous Read Mode Reset (FFh or FFFFh) For Fast Read Dual/Quad I/O operations, “Continuous Read Mode” Bits (M7-0) are implemented to further reduce instruction overhead. By setting the (M7-0) to “Ax” hex, the next Fast Read Dual/Quad I/O operation ...
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ELECTRICAL CHARACTERISTICS 11.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. This device has been designed and tested for the specified operation ...
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Power-u p Timing and Write In PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. hibit Thre shold SYM (1) VSL ...
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DC Electrical Characteristics PARAMETER SYMBOL IN (1) Input Capacitance C (1) Output Capacitance Cout Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL ...
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AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions, except Read Data (03h) & Octal Word Read (E3h) 2.7V-3.6V VCC & Industrial Temperature Clock frequency for Octal Word Read Quad I/O (E3h) 3.0V-3.6V VCC & Industrial Temperature Clock freq. ...
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AC Electrical Characteristics ( DESCRIPTION /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z /HOLD to Output High-Z Write Protect Setup ...
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Serial Output Timing 11.9 Input Timing 11.10 Hold Timing - 52 - W25Q16V ...
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PACKAGE SPECIFICATION 12.1 8-Pin SOIC 208-mil (Package Code SS) SYMBOL MIN A 1.75 A1 0.05 A2 1.70 b 0.35 C 0.19 D 5.18 D1 5.13 E 5. 7. θ 0° Notes: ...
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WSON (Package Code ZP) SYMBOL MIN A 0.70 A1 0. 5.90 D2 3.35 4. (2) L 0.55 y 0.00 MILLIMETERS TYP. MAX MIN 0.75 0.80 0.0275 0.02 ...
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WSON Cont’d. SYMBOL Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not ...
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SOIC 300-mil (Package Code SF) SYMBOL MIN A 2. 0.33 C 0.18 D 10.08 E 10. 0.38 y θ Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC ...
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... ORDERING INFORMATION W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I 16M-bit V = 2. 8-pin SOIC 208-mil SF = 16-pin SOIC 300-mil I = Industrial (-40°C to +85°C) ( Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb Notes: nd 1a. Only the 2 letter is used for the part marking; WSON package type ZP is not used for the part marking. ...
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... PACKAGE TYPE DENSITY SS 16M-bit SOIC-8 208mil SF 16M-bit SOIC-16 300mil (1) ZP 16M-bit WSON-8 6x5mm Note: 1. WSON package type ZP is not used in the top side marking. PRODUCT NUMBER W25Q16VSSIG W25Q16VSFIG W25Q16VZPIG - 58 - W25Q16V TOP SIDE MARKING 25Q16VSIG 25Q16VFIG 25Q16VIG ...
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... Added Mode Bit Reset instruction and description. Added note for SRP1,0 status during Power Lock- Down protection. Updated Status Register memory protection tables. Added note for Power Lock-Down, OTP functions. Added note for 64 Bit unique ID. Added note for 32KB/64KB block erase command. ...
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... Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life ...