M45PE80-VMW6TG NUMONYX, M45PE80-VMW6TG Datasheet - Page 14

• Manufacturer Part Number: M45PE80-VMW6TG
• Description: IC FLASH 8MBIT 25MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMW6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 25MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMW6TG; M45PE80-VMW6TGTR

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Status Register
The Status Register contains two status bits that can be read by the Read Status Register
(RDSR) instruction. See
description of the Status Register bits.
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M45PE80 boasts the following data protection mechanisms:
Power-On Reset and an internal timer (t
inadvertent changes while the power supply is outside the operating specification.
Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
The Hardware Protected mode is entered when Write Protect (W) is driven Low,
causing the first 256 pages of memory to become read-only. When Write Protect (W) is
driven High, the first 256 pages of memory behave like the other pages of memory
The Reset (Reset) signal can be driven Low to protect the contents of the memory
during any critical time, not just during Power-up and Power-down.
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
Power-up
Reset (RESET) driven Low
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
Section 6.4: Read Status Register (RDSR)
PUW
) can provide protection against
for a detailed