M25PE16-VMP6TG NUMONYX, M25PE16-VMP6TG Datasheet - Page 43

• Manufacturer Part Number: M25PE16-VMP6TG
• Description: IC FLASH 16MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE16-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: MLP EP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PE16-VMP6TGCT

M25PE16
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V
power on reset (POR) threshold voltage, V
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page write (PW), page program (PP),
page erase (PE), sector erase (SE), subsector erase (SSE), bulk erase (BE), write status
register (WRSR) and write to lock register (WRLR) instructions until a time delay of t
has elapsed after the moment that V
operation of the device is not guaranteed if, by this time, V
write, program or erase instructions should be sent until the later of:
These values are specified in
If the delay, t
selected for read instructions even if the t
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the power-up and power-down phases.
At power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
Each device in a system should have the V
the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V
(POR) threshold voltage, V
to any instruction. The designer needs to be aware that if a power-down occurs while a
write, program or erase cycle is in progress, some data corruption can result.
V
V
t
t
The device is in the standby mode (not the deep power-down mode).
The write enable latch (WEL) bit is reset.
The write in progress (WIP) bit is reset
The lock registers are reset (write lock bit, lock down bit) = (0, 0)
PUW
VSL
CC
SS
(min) at power-up, and then for a further delay of t
at power-down
after V
after V
VSL
, has elapsed, after V
CC
CC
passed the V
passed the V
CC
WI
drops from the operating voltage, to below the power on reset
, all operations are disabled and the device does not respond
Table
CC
CC
) until V
WI
Section 3: SPI
(min) level
11.
threshold
CC
CC
rises above the V
has risen above V
CC
PUW
CC
WI
reaches the correct value:
– all operations are disabled, and the device
line decoupled by a suitable capacitor close to
delay is not yet fully elapsed.
modes.
WI
CC
VSL
CC
threshold. However, the correct
is still below V
(min), the device can be
Power-up and power-down
CC
CC
is less than the
CC
(min). No
supply.
PUW
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