M95080-WMN6P STMicroelectronics, M95080-WMN6P Datasheet - Page 8

• Manufacturer Part Number: M95080-WMN6P
• Description: IC EEPROM 8KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95080-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 8K (1K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 1024 X 8
• Interface Type: Serial, SPI
• Clock Frequency: 10MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SO
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8605-5; M95080-WMN6P

M95160, M95080
OPERATING FEATURES
Power-up
When the power supply is turned on, V
from V
During this time, the Chip Select (S) must be al-
lowed to follow the V
lowed to float, but should be connected to V
a suitable pull-up resistor.
As a built-in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Device Internal Reset
In order to prevent inadvertent Write operations
during Power-up, a Power On Reset (POR) circuit
is included. At Power-up (continuous rise up of
V
until the V
threshold voltage (this threshold is lower than the
minimum V
10,
POR threshold, the device is reset and is the fol-
lowing state:
–
–
–
Status register state:
–
–
The SRWD, BP1 and BP0 bits of the Status Reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
Prior to selecting and issuing instructions to the
memory, a valid and stable V
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (t
8/39
CC
11
Standby Power mode
deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started).
not in the Hold Condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
), the device will not respond to any instruction
SS
and 13). When V
to V
CC
CC
CC
has reached the Power On Reset
operating voltage defined in Tables
.
CC
voltage. It must not be al-
W
CC
).
has passed over the
CC
voltage must be
CC
CC
rises
via
At Power-down (continuous decay of V
soon as V
age, below the Power On Reset threshold voltage,
the device stops responding to any instruction sent
to it.
Power-down
At Power-down, the device must be deselected
and in Standby Power mode (i.e. no internal Write
cycle in progress). Chip Select (S) should be al-
lowed to follow the voltage applied on V
Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode. The device
consumes I
19.
When Chip Select (S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes into the Standby
Power mode, and the device consumption drops
to I
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low.
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
CC1
.
CC
CC
drops from the normal operating volt-
, as specified in
Table 14.
CC
to
CC
.
Table
), as