M24C04-WMN6P STMicroelectronics, M24C04-WMN6P Datasheet - Page 10

• Manufacturer Part Number: M24C04-WMN6P
• Description: IC EEPROM 4KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24C04-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 512 x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Capacitance, Input: 8 pF (SDA), 6 pF (Other Pins)
• Current, Input, Leakage: ±2 μA
• Current, Operating: 2 mA
• Current, Output, Leakage: ±2
• Current, Supply: 3 mA
• Data Retention: >40 yrs.
• Density: 4K
• Package Type: SO8
• Temperature, Operating: -40 to +85 °C
• Temperature, Operating, Maximum: 85 °C
• Temperature, Operating, Minimum: -40 °C
• Time, Access: 900 ns
• Time, Fall: 50 ns
• Time, Rise: 50 ns
• Voltage, Esd: 4000 V
• Voltage, Input, High: 3.5 to 6.5 V
• Voltage, Input, High Level: 0.7 V
• Voltage, Input, Low: 0.75 to 1.65 V
• Voltage, Input, Low Level: –0.45 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.5 to 5.5 V
• Memory Configuration: 512 X 8
• Clock Frequency: 400kHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8562; M24C04-WMN6P

M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
15.
make use of this, a polling sequence can be used
by the bus master.
The sequence, as shown in
10/29
to
Table
First byte of instruction
with RW = 0 already
decoded by the device
17., but the typical time is shorter. To
ReSTART
STOP
Figure
w
NO
) is shown in
NO
8., is:
DEVICE SELECT
START Condition
WRITE Cycle
Addressing the
in Progress
with RW = 0
Operation is
Returned
Memory
ACK
Next
YES
Table
WRITE Operation
WRITE Operation
DATA for the
Continue the
YES
NO
–
–
–
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
and Receive ACK
Send Address
Condition
START
Random READ Operation
DEVICE SELECT
Continue the
with RW = 1
YES
AI01847C