CY14B256L-SZ45XIT Cypress Semiconductor Corp, CY14B256L-SZ45XIT Datasheet - Page 3

IC NVSRAM 256KBIT 45NS 32SOIC

CY14B256L-SZ45XIT

Manufacturer Part Number
CY14B256L-SZ45XIT
Description
IC NVSRAM 256KBIT 45NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr

Specifications of CY14B256L-SZ45XIT

Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
256K (32K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SOIC (7.5mm Width)
Word Size
8b
Organization
32Kx8
Density
256Kb
Interface Type
Parallel
Access Time (max)
45ns
Operating Supply Voltage (typ)
3.3V
Package Type
SOIC
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
-40C to 85C
Pin Count
32
Mounting
Surface Mount
Supply Current
55mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY14B256L-SZ45XIT
Manufacturer:
2002+
Quantity:
6 235
Pin Configurations
Pin Definitions
Document Number: 001-06422 Rev. *I
Pin Name
DQ
A
V
HSB
0
V
V
WE
CE
OE
NC
0
–A
CAP
SS
CC
-DQ
14
7
Alt
W
E
G
No Connect
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
Power Supply Power Supply Inputs to the Device.
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
IO Type
Ground
Input
Input
Input
Input
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
No Connect. This pin is not connected to the die.
Description
CY14B256L
Page 3 of 19
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