CY7C1426AV18-167BZXC Cypress Semiconductor Corp, CY7C1426AV18-167BZXC Datasheet - Page 22

• Manufacturer Part Number: CY7C1426AV18-167BZXC
• Description: IC SRAM 36MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1426AV18-167BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (4M x 9)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number: 38-05614 Rev. *C
Switching Characteristics
Parameter
t
t
t
t
t
t
Set-up Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
Notes:
25. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency,
26. This part has a voltage regulator internally; t
27. For D2 data signal on CY7C1426AV18 device, t
28. t
29. At any given voltage and temperature t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
Cypress
[27]
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
can be initiated.
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
Parameter
V
Access
K Clock and C Clock Cycle
Time
Input Clock (K/K; C/C)
HIGH
Input Clock (K/K; C/C)
LOW
K Clock Rise to K Clock
Rise and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C
Clock Rise (rising edge to
rising edge)
Address Set-up to K Clock
Rise
Control Set-up to K Clock
Rise (RPS, WPS)
Double Data Rate Control
Set-up to Clock (K, K) Rise
(BWS
BWS
D
Rise
Address Hold after K Clock
Rise
Control Hold after K Clock
Rise (RPS, WPS)
Double Data Rate Control
Hold after Clock (K, K) Rise
(BWS
BWS
D
(K/K) Rise
C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
DD
[X:0]
[X:0]
(Typical) to the First
3
3
Set-up to Clock (K/K)
0
0
Hold after Clock
)
)
, BWS
, BWS
CHZ
Description
[29]
Over the Operating Range
POWER
is less than t
1,
1,
SD
BWS
BWS
is the time that the power needs to be supplied above V
is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.
CLZ
2
2
,
,
and t
CHZ
–0.45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
3.30 5.25 3.60 5.25
1.32
1.32
1.49
0.0
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
300 MHz
1
less than t
[24, 25]
1.45
0.45
–
–
–
–
–
–
–
–
–
–
–
–
CO
.
–0.45
1.4
1.4
1.6
0.0
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
278 MHz
1
1.55
0.45
–
–
–
–
–
–
–
–
–
–
–
–
–0.45
0.35
0.35
0.35
0.35
4.0
1.6
1.6
1.8
0.0
0.5
0.5
0.5
0.5
250 MHz
1
–
DD
minimum initially before a Read or Write operation
0.45
6.3
1.8
–
–
–
–
–
–
–
–
–
–
–
–
–0.45
200 MHz
5.0
2.0
2.0
2.2
0.0
0.6
0.6
0.4
0.4
0.6
0.6
0.4
0.4
1
–
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
CY7C1411AV18
0.45
2.2
7.9
–
–
–
–
–
–
–
–
–
–
–
–0.50
0.0
167 MHz
6.0
2.4
2.4
2.7
0.7
0.7
0.5
0.5
0.7
0.7
0.5
0.5
1
–
Page 22 of 28
0.50
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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