CY7C1360C-166AXIT Cypress Semiconductor Corp, CY7C1360C-166AXIT Datasheet - Page 25
![IC SRAM 9MBIT 166MHZ 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C1360C-166AXIT
Manufacturer Part Number
CY7C1360C-166AXIT
Description
IC SRAM 9MBIT 166MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1360C-200AJXC.pdf
(34 pages)
Specifications of CY7C1360C-166AXIT
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1360C-166AXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Notes
Document Number: 38-05540 Rev. *K
Data Out (Q)
28. On this diagram, when CE is LOW: CE
29. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data In (D)
ADDRESS
ADSC
ADSP
BWE,
ADV
BW
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t CL
t DS
Single WRITE
D(A1)
(continued)
t ADH
t DH
1
is LOW, CE
A2
2
Figure 7. Write Cycle Timing
is HIGH and CE
D(A2)
DON’T CARE
D(A2 + 1)
t WES
3
is LOW. When CE is HIGH: CE
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
X
ADV suspends burst
LOW.
[28, 29]
D(A2 + 2)
ADSC extends burst
1
is HIGH or CE
D(A2 + 3)
CY7C1360C, CY7C1362C
t ADS
2
is LOW or CE
A3
D(A3)
t ADH
t
ADVS
t WES
Extended BURST WRITE
D(A3 + 1)
3
t
t WEH
ADVH
is HIGH.
D(A3 + 2)
Page 25 of 34
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