W25X40VSSIG Winbond Electronics, W25X40VSSIG Datasheet
W25X40VSSIG
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W25X40VSSIG Summary of contents
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... AND 8M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI W25X10, W25X20, W25X40, W25X80 Publication Release Date: September 22, 2006 - 1 - Preliminary - Revision I ...
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... Write Enable Latch (WEL) ............................................................................................11 10.1.3 Block Protect Bits (BP2, BP1, BP0)..............................................................................11 10.1.4 Top/Bottom Block Protect (TB) .....................................................................................11 10.1.5 Reserved Bits ...............................................................................................................11 10.1.6 Status Register Protect (SRP) ......................................................................................12 10.1.7 Status Register Memory Protection ..............................................................................13 10.2 INSTRUCTIONS........................................................................................................... 14 10.2.1 Manufacturer and Device Identification.........................................................................14 10.2.2 Instruction Set 10.2.3 Write Ensable (06h)......................................................................................................16 10.2.4 Write Disable (04h) ...
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Read Status Register (05h) ..........................................................................................17 10.2.6 Write Status Register (01h) ..........................................................................................18 10.2.7 Read Data (03h) ...........................................................................................................19 10.2.8 Fast Read (0Bh) ...........................................................................................................20 10.2.9 Fast Read Dual Output (3Bh) .......................................................................................21 10.2.10 Page Program (02h) ...................................................................................................22 10.2.11 Sector Erase (20h) .....................................................................................................23 10.2.12 ...
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... Single 2.7 to 3.6V supply – 5mA active current, 1µA Power-down (typ) – -40° to +85°C operating range • Software and Hardware Write Protection – Write-Protect all or portion of memory – Enable/Disable protection with /WP pin – Top or bottom array protection • Space Efficient Packaging – ...
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PIN CONFIGURATION SOIC 150-MIL Figure 1a. W25X10, W25X20 and W25X40 Pin Assignments, 8-pin SOIC (Package Code SN) 4. PIN CONFIGURATION SOIC 208-MIL Figure 1b。W25X40 and W25X80 Pin Assignments, 8-pin SOIC (Package Code SS) 5. PIN CONFIGURATION PDIP 300-MIL Figure ...
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PIN CONFIGURATION WSON 6X5-MM Figure 1d。W25X10, W25X20, W25X40 and W25X80 Pin Assignments, 8-pin WSON (Package Code ZP) 7. PIN DESCRIPTION SOIC 150-mil, SOIC 208-mil, PDIP 300-mil, and WSON 6x5-mm PAD NO. PAD NAME 1 / /WP ...
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... The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. ...
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BLOCK DIAGRAM Figure 2. W25X10, W25X20, W25X40 and W25X80 Block Diagram W25X10, W25X20, W25X40, W25X80 - 8 - ...
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... The W25X10/20/40/80 supports Dual output operation when using the "Fast Read with Dual Output" (3B hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice the rate possible with the standard SPI. This instruction is ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM for execution ...
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... Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... CONTROL AND STATUS REGISTERS The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, and the state of write protection. The Write Status Register instruction can be used to configure the devices write protection features. See Figure 3. ...
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Status Register Protect (SRP) The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the ...
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... Status Register Memory Protection (1) STATUS REGISTER TB BP2 BP1 BP0 (1) STATUS REGISTER TB BP2 BP1 BP0 (1) STATUS REGISTER TB BP2 BP1 BP0 (1) STATUS REGISTER TB BP2 BP1 BP0 Note don’t care W25X10, W25X20, W25X40, W25X80 W25X80 (8M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE ...
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... Write, Program or Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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... A15–A8 A7–A0 (D7–D0) A15–A8 A7–A0 A15–A8 A7–A0 dummy dummy (ID7-ID0) dummy 00h (M7-M0) (ID15-ID8) (ID7-ID0) Memory Capacity Type Publication Release Date: September 22, 2006 - 15 - BYTE 6 N-BYTES (2) (Next byte) continuous (Next Byte) (D7–D0) continuous I/O = (one byte (D6,D4,D2,D0) per 4 clocks, ...
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Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip ...
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Read Status Register (05h) The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge ...
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... The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0 set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table). The Write Status Register instruction also allows the Status Register Protect bit (SRP set ...
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... DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in figure 8 ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F eight “dummy” clocks after the 24-bit address as shown in figure 9. The ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DO and DIO, instead of just DO. This allows data ...
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... Page Program (02h) The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, obtain the devices electronic identification (ID) number or do ...
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W25X10, W25X20, W25X40, W25X80 Figure 17. Release Power-down / Device ID Instruction Sequence Diagram - 28 - ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...
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... JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 19. For memory type and capacity values refer to Manufacturer and Device Identification table. ...
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ELECTRICAL CHARACTERISTICS (P 11.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside ...
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Endurance and Data Retention PARAMETER Erase/Program Cycles 4KB sector, 64KB block or full chip. Data Retention Full Temperature Range 11.4 Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit ...
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DC Electrical Characteristics PARAMETER SYMBOL Input Capacitance C (1) IN Output Capacitance Cout (1) Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / Dual Output Read ...
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AC Measurement Conditions PARAMETER Load Capacitance Load Capacitance for FR only 1 Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data ...
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AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature Clock frequency for all instructions, except Read Data (03h) 3.0V-3.6V VCC & Commercial Temperature Clock frequency, for Fast Read (0Bh, 3Bh) ...
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AC Electrical Characteristics ( DESCRIPTION /HOLD Active Setup Time relative to CLK /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z ...
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Serial Output Timing 11.10 Input Timing 11.11 Hold Timing W25X10, W25X20, W25X40, W25X80 Publication Release Date: September 22, 2006 - 37 - Preliminary - Revision I ...
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PACKAGE SPECIFICATION 12.1 8-Pin SOIC 150-mil (Package Code SN) SYMBOL MIN A 1.47 A1 0.10 A2 --- b 0.33 C 0.19 D (3) 4.80 E 5.80 E1 (3) 3.80 e (2) L 0.40 θ --- Notes: ...
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SOIC 208-mil (Package Code SS) SYMBOL θ y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and ...
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PDIP 300-mil (Package Code DA Symbol α ...
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WSON W25X10, W25X20, W25X40, W25X80 Publication Release Date: September 22, 2006 - 41 - Preliminary - Revision I ...
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WSON Cont’d. W25X10, W25X20, W25X40, W25X80 - 42 - ...
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ORDERING INFORMATION Notes: 1a. The Winbond W25X20, W25X40 and W25X80 are fully compatible with the previous Nexflash NX25X20, NX25X40 and NX25X80 Serial Flash Memories. 1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such ...
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REVISION HISTORY VERSION DATE A 06/28/05 B 09/26/05 C 01/09/06 D 09/26/05 E 02/13/06 F 05/11/06 G 06/06/06 H 06/22/06 I 09/22/06 W25X10, W25X20, W25X40, W25X80 PAGE New Create Updated datasheet to comply with Winbond ALL Standard Updated hex values ...
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... Publication Release Date: September 22, 2006 - 45 - ranteed. Winbond Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Preliminary - Revision I ...