W25B40VSNIG T&R Winbond Electronics, W25B40VSNIG T&R Datasheet
W25B40VSNIG T&R
Specifications of W25B40VSNIG T&R
Related parts for W25B40VSNIG T&R
W25B40VSNIG T&R Summary of contents
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... SERIAL FLASH MEMORY WITH BOOT AND PARAMETER SECTORS Formally NexFlash NX25B40 The Winbond W25B40 / W25B40A is fully compatible with the previous NexFlash NX25B40 Serial Flash memory. W25B40/W25B40A Publication Release Date: September 22, 2006 - 1 - Revision N ...
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Table of Contents- 1. GENERAL DESCRIPTION ......................................................................................................... 4 2. FEATURES ................................................................................................................................. 4 3. PIN CONFIGURATION ............................................................................................................... 5 4. PIN DESCRIPTION..................................................................................................................... 5 4.1 Package Types ............................................................................................................... 5 4.2 Chip Select (/CS) ............................................................................................................ 5 4.3 Serial Data Output (DO) ................................................................................................. 6 4.4 ...
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Read Data (03h) .............................................................................................................17 8.2.8 Fast Read (0Bh) .............................................................................................................18 8.2.9 Page Program (02h) .......................................................................................................19 8.2.10 Sector Erase (D8h).......................................................................................................20 8.2.11 Chip Erase (C7h)..........................................................................................................21 8.2.12 Power-down (B9h) ........................................................................................................22 8.2.13 Release Power-down / Device ID (ABh) .......................................................................23 8.2.14 Read Manufacturer / Device ...
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... GENERAL DESCRIPTION The W25B40 / W25B40A is a 4Mb (512KB) Serial Flash Memory with erasable sectors that allows for boot code and parameter storage. The W25B40 / W25B40A is packaged in an 8-pin SOIC 150-mil and is compatible with the standard W25P40 specification with the following exceptions. ...
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PIN CONFIGURATION Figure 1. W25B40 / W25B40A Pin Assignments, 8-pin SOIC (Package Code SN) 4. PIN DESCRIPTION PIN NO. PIN NAME 1 / /WP 4 GND CLK 7 /HOLD 8 VCC 4.1 Package ...
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... The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. ...
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BLOCK DIAGRAM (BOTTOM BOOT) Figure 2a. W25B40 / W25B40A Block Diagram for Bottom Boot Sector Organization W25B40/W25B40A Publication Release Date: September 22, 2006 - 7 - Revision N ...
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BLOCK DIAGRAM (TOP BOOT-SPECIAL ORDER) Figure 2b. W25B40 / W25B40A Block Diagram for Top Boot Sector Organization (Special Order) W25B40/W25B40A - 8 - ...
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... WRITE PROTECTION Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the W25B40 / W25B40A provides several means to protect data from inadvertent writes. ...
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... Status Register Protect (SRP) and Block Protect (BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). ...
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... Write, Program or Erase must complete on a byte boundary (/CS) driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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Manufacturer and Device Identification MANUFACTURER ID Winbond Serial Flash Device ID W25B40 / W25B40A (Bottom Boot) W25B40 / W25B40A (Top Boot) (1) 8.2.2 Instruction Set INSTRUCTION BYTE 1 BYTE 2 NAME CODE Write Enable 06h Write Disable 04h Read ...
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Write Disable (04h) The Write Disable instruction (Figure 4) resets the Write Enable Latch (WEL) bit in the Status Register The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into ...
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Read Status Register (05h) The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” into the DI pin on the rising edge ...
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... The Write Status Register instruction allows the Block Protect bits (BP2, BP1 and BP0 set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table). The Write Status Register instruction also allows the Status Register Protect bit (SRP set ...
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... DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F “dummy” byte after the 24-bit address as shown in figure 9. The dummy ...
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... Page Program (02h) The Page Program instruction allows from one byte to 256 bytes of data to be programmed at memory locations previously erased to all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... Sector Erase (D8h) The Sector Erase instruction sets all memory within a specified sector to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Erase Sector Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, obtain the devices electronic identification (ID) number or do ...
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Figure 15. Release Power-down / Device ID Instruction Sequence Diagram - 24 - W25B40/W25B40A ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...
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ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1 This device has been designed and tested for the specified operation ranges. Proper operation outside of ...
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Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL t (1) VSL t (1) PUW V (1) WI Figure ...
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DC Electrical Characteristics (Preliminary) PARAMETER SYMBOL Input Capacitance C (2) IN Output Capacitance Cout (2) Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL ...
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AC Electrical Characteristics (Preliminary) DESCRIPTION Clock frequency, for Fast Read (0Bh) and all other instructions except Read Data (03h) 2.7V-3.6V VCC (25B40A / 25B40) 3.0V-3.6V VCC Clock freq. Read Data instruction (03h) 2.7V-3.6V VCC 3.0V-3.6V VCC (for sequential read ...
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AC Electrical Characteristics (Preliminary) DESCRIPTION /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z /HOLD to Output High-Z Write Protect Setup ...
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Serial Output Timing 9.9 Input Timing 9.10 Hold Timing W25B40/W25B40A - 32 - ...
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PACKAGE SPECIFICATION 10.1 8-Pin SOIC 150-mil (Package Code SN) SYMBOL MIN A 1.47 A1 0.10 A2 --- b 0.33 C 0.19 D (3) 4.80 E 5.80 E1 3.80 (3) e (2) L 0.40 θ --- Notes: ...
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ORDERING INFORMATION 2. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T), when placing orders. 3. The “W” prefix is not included on the part marking. W25B40/W25B40A (2), ...
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... Updated and improved AC Parameters in and changed CHSH CLQV (2.7V-3.6V / 3.0V-3.6V) for consistency with other spiFlash memory data sheets. Updated Important Notice Changed NexFlash part numbers to Winbond part numbers and updated ordering and contact information Updated data sheet to comply with Winbond standard. Updated FR and f ...
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... TEL: 81-45-4781881 FAX: 81-45-4781800 - 36 - W25B40/W25B40A ranteed. Winbond Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 ...