CY62256L-70PXC Cypress Semiconductor Corp, CY62256L-70PXC Datasheet

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CY62256L-70PXC

Manufacturer Part Number
CY62256L-70PXC
Description
IC SRAM 256KBIT 70NS 28DIP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62256L-70PXC

Format - Memory
RAM
Memory Type
SRAM
Memory Size
256K (32K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-1782
Cypress Semiconductor Corporation
Document #: 001-02367 Rev. **
Features
Functional Description
The CY6264 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
HIGH chip enable (CE
and three-state drivers. Both devices have an automatic
• 55, 70 ns access times
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Logic Block Diagram
features
CE
CE
WE
OE
1
2
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
2
), and active LOW output enable (OE)
COLUMN DECODER
INPUT BUFFER
256 x 32 x 8
ARRA Y
1
, CE
2
, and OE
1
3901 North First Street
POWER
DOWN
), an active
power-down feature (CE
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
inputs are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
0
through A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
San Jose
2
active HIGH, while WE remains inactive or
12
). Reading the device is accomplished by
0
through I/O
,
1
8K x 8 Static RAM
), reducing the power consumption
CA 95134
Pin Configuration
2
GND
is HIGH, data on the eight data
I/O
I/O
I/O
A
A
A
NC
A
A
A
A
A
A
10
11
12
4
5
6
7
8
9
0
1
2
7
) is written into the memory
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
Revised June 27, 2005
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
408-943-2600
V
WE
CE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
3
2
1
0
7
6
5
4
3
CY6264
2
1
1
1
and WE
and OE

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CY62256L-70PXC Summary of contents

Page 1

... COLUMN DECODER Cypress Semiconductor Corporation Document #: 001-02367 Rev. ** power-down feature (CE by over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When and inputs are both LOW and CE input/output pins (I/O ...

Page 2

Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current Shaded areas contain advance information. Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature ...

Page 3

... At any given temperature and voltage condition The internal write time of the memory is defined by the overlap of CE signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...

Page 4

AC Test Loads and Waveforms R1 481Ω 5V OUTPUT OUTPUT 255Ω INCLUDING JIG AND SCOPE (a) Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT Switching Waveforms [8, 9] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [10, ...

Page 5

Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) ADDRESS DATA IN DATA I/O DATA UNDEFINED Write Cycle No. 2 (CE Controlled) ADDRESS DATA IN DATA I/O ...

Page 6

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 1.0 0.8 0.6 0.4 0 0.0 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.3 1.2 1.1 ...

Page 7

Truth Table Address Designators Address Name A10 A11 A12 Document ...

Page 8

Ordering Information Speed (ns) Ordering Code 55 CY6264-55SC 70 CY6264-70SC 55 CY6264-55SNC 55 CY6264-55SNXC 70 CY6264-70SNC 70 CY6264-70SNXC 70 CY6264-70SNI 70 CY6264-70SNXI Shaded areas contain advance information. Package Diagrams 28-lead (300 mil) SNC Package Outline (Narrow Body) SN28 0.702 0.710 ...

Page 9

... Document #: 001-02367 Rev. ** © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 10

Document History Page Document Title:CY6264 Static RAM Document Number: 001-02367 REV. ECN NO. Issue Date ** 384870 See ECN Document #: 001-02367 Rev. ** Orig. of Change Description of Change PCI Spec # change from 38-00425 to ...

Page 11

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