TE28F320C3TD70A NUMONYX, TE28F320C3TD70A Datasheet
TE28F320C3TD70A
Specifications of TE28F320C3TD70A
TE28F320C3TD70
Related parts for TE28F320C3TD70A
TE28F320C3TD70A Summary of contents
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... Flash Data Integrator (FDI) software and you have a cost- effective, flexible, monolithic code plus data storage solution. Intel Memory (C3) products will be available in 48-lead TSOP, 48-ball CSP, and 64-ball Easy BGA packages. Additional information on this product family can be obtained by accessing the Intel Flash website: http://www ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE ...
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... Document Purpose ...............................................................................................................7 1.2 Nomenclature .......................................................................................................................7 1.3 Conventions..........................................................................................................................7 2.0 Device Description ........................................................................................................................8 2.1 Product Overview .................................................................................................................8 2.2 Ballout Diagram ....................................................................................................................8 2.3 Signal Descriptions .............................................................................................................13 2.4 Block Diagram ....................................................................................................................14 2.5 Memory Map .......................................................................................................................15 3.0 Device Operations .......................................................................................................................17 3.1 Bus Operations ...................................................................................................................17 3.1.1 Read ......................................................................................................................17 3.1.2 Write ......................................................................................................................17 3.1.3 Output Disable .......................................................................................................17 3.1.4 Standby..................................................................................................................18 3.1.5 Reset .....................................................................................................................18 4.0 Modes of Operation ...
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Contents 5.6.1 Program Protection................................................................................................ 31 6.0 Power Consumption.................................................................................................................... 32 6.1 Active Power (Program/Erase/Read).................................................................................. 32 6.2 Automatic Power Savings (APS) ........................................................................................ 32 6.3 Standby Power ................................................................................................................... 32 6.4 Deep Power-Down Mode.................................................................................................... 32 6.5 Power and Reset Considerations ....................................................................................... 33 6.5.1 Power-Up/Down ...
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... V Maximum Specification change (Section 4. test conditions clarification (Section 4.3) CCS Added Command Sequence Error Note (Table 7) Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory Family. Added t /t and t (Section 4.6) BHWH BHEH QVBL Programming the Protection Register clarification (Section 3.4.2) ...
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Contents Date of Version Revision 4/05/02 -014 3/06/03 -016 10/03 -017 6 Description Updated 64Mb product offerings. Updated 16Mb product offerings. Revised and corrected DC Characteristics Table. Added mechanicals for Easy BGA. Minor text edits throughout document. Complete technical update. ...
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... Clear: When referring to registers, the term clear means the bit is a logical 0. Block: A group of bits (or words) that erase simultaneously with one block erase instruction. Main Block: A block that contains 32 Kwords. Parameter Block: A block that contains 4 Kwords. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) ® Advanced+ Boot Block Flash Memory 7 ...
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... Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks. The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase and program operations VPP ...
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... Figure 1. 48-Lead TSOP Package WE NOTES: 1. For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on Pins 9 and 10. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3 Advanced+ Boot Block 11 48-Lead TSOP TOP VIEW CCQ 46 GND OE# ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 2. Mark for Pin-1 indicator on 48-Lead 8Mb, 16Mb and 32Mb TSOP Current Mark: New Mark: Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel 48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the white triangle will continue to use a dimple as a Pin 1 indicator ...
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... GND D7 NOTES: 1. Shaded connections indicate the upgrade address connections. Routing is not recommended in this area. 2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 3. Unused address balls are not populated. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) 1,2 16M A8 VPP WP# ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 4. 64-Ball Easy BGA Package ( RP WP SSQ ( CCQ CC SSQ Top View - Ball Side NOTES: 1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 2. Unused address balls are not populated GND ( ( SSQ ...
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... CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense CE# INPUT amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 2.4 Block Diagram V CCQ A[MAX:MIN] Input Buffer Address Latch Address Counter Output Buffer Identifier Register Status Register Power Data Reduction Comparator Control Y-Decoder Y-Gating/Sensing X-Decoder Input Buffer I/O Logic CE# Command WE# User OE# Interface RP# ...
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... The bulk of the array is divided into 32 Kword main blocks that can store code or data, and 4 Kword boot blocks to facilitate storage of boot code or for frequently changing small parameters. See Table 3, “Top Boot Memory Map” on page 15 Map” on page 16 for details. ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 4. Bottom Boot Memory Map 8-Mbit Size Memory Size Blk Blk (KW) Addressing (KW) (HEX 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 32 ... ... ... ... 32 10 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 4 16 16-Mbit Memory Size Blk ...
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... NOTE Don’t Care (V 3.1.1 Read When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted. CE# is the device selection control; when active low, it enables the flash memory device. OE# is the data output control; when low, data is output on DQ[15:0]. See Waveform” on page 3.1.2 Write A write cycle occurs when both CE# and WE# are low ...
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... Figure 10, “Reset Operations Waveforms” on page If RP# is taken low for time t aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: 1 ...
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... Read Mode The flash memory has four read modes (read array, read identifier, read status, and CFI query), and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 6. Device Identification Codes Item Manufacturer ID Device ID 2 Block Lock Status Block Lock-Down Status Protection Register Lock Status Protection Register NOTES: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i ...
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... Clear the status register before beginning another command or sequence. The Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the Status Register. ...
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... The only other valid commands while program is suspended are Read Status Register, Read Identifier, CFI Query, and Program Resume. After the Program Resume command is issued to the flash memory, the WSM will continue with the programming process and status register bits SR[2] and SR[7] will automatically be cleared. ...
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... Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase - sequence interruption in order to read data from—or program data to— another block in memory. Once the erase sequence is started, issuing the Erase Suspend command to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the Erase operation has been suspended ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 7. Command Bus Operations Command Read Array Read Identifier CFI Query Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program X = "Don’t Care" ...
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... WSM to execute the Protection Program algorithm to the protection register. The flash outputs Set-Up status-register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Command Description 21. Section 4.3, “Erase Mode” on page Section 5.1) . See Sections 3.2.5.1 and 3.2.6.1. ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 8. Command Codes and Descriptions Code Device Mode (HEX) 10 Alt. Prog Set-Up Operates the same as Program Set - up command. (See 0x40/Program Set-Up) Invalid/ Unassigned commands should not be used. Intel reserves the right to redefine these codes for ...
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... D0 indicates block lock status ‘0’, block is unlocked ‘1’, block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) displays all of the possible locking states. Locked- Locked Down [X01] ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 5.1.1 Locking Operation The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which will be described in the following sections. See page 27 and Figure 17, “Locking Operations Flowchart” on page The following concisely summarizes the locking functionality. ...
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... CPU or ASIC, preventing device substitution. The Intel application note, AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains additional application information. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 5.5.1 Reading the Protection Register The protection register is read in the read-identifier mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Figure 6, “Protection Register array mode, issue the Read Array command (0xFF) ...
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... V Fast Programming Absolute Write Protection With V Low Voltage and 12 V Fast Programming NOTE resistor can be used if the V Designing with the Advanced+ Boot Block Flash Memory Architecture for details. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) programming voltage can be held low for absolute ...
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... Automatic Power Savings (APS) Automatic Power Savings provides low - power operation during read mode. After data is read from the memory array and the address lines are idle, APS circuitry places the device in a mode where typical current is comparable to I new location is read. ...
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... The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 6.6 Power Supply Decoupling Flash memory power-switching characteristics require careful device decoupling. System designers should consider the following three supply current issues: • Standby current levels (I • Read current levels (I • Transient peaks produced by falling and rising edges of CE#. ...
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... V 80 hours maximum. 7.3 DC Current Characteristics Table 11. DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output Leakage I LO Current Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Parameter Notes may be connected for a total 2.7 V–3.6 V 2.7 V–2. 2.7 V–3.6 V 1.65 V– ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 11. DC Current Characteristics (Sheet Sym Parameter V Standby Current CC for 0.13 and 0.18 Micron Product I CCS V Standby Current CC for 0.25 Micron Product V Power-Down CC Current for 0.13 and 0.18 Micron Product I CCD V Power-Down CC Current for 0.25 ...
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... If device is read while in erase suspend, current draw CCES CCWS is sum of I and I CCES and I . CCR Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) V 2.7 V–3.6 V 2.7 V–2. 2.7 V–3.6 V 1.65 V–2.5 V CCQ Note Typ Max Typ ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 7.4 DC Voltage Characteristics Table 12. DC Voltage Characteristics V 2.7 V–3 Sym Parameter V 2.7 V–3.6 V CCQ Note Min Input Low V –0.4 IL Voltage Input High V 2.0 IH Voltage Output Low V –0.1 OL Voltage Output High V CCQ V OH Voltage –0.1V ...
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... GLQV 2. Sampled, but not 100% tested. 3. See Figure 8, “Read Operation Waveform” on page 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Density Product 3.0 V – 3.6 V 2.7 V – 3 Note Min Max ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 14. Read Operations—16 Mbit Density Density 70 ns Product Para- # Sym mete r 2.7 V–3 Min Read Cycle Time AVAV t Address to AVQ R2 Output Delay V t CE# to Output ELQ R3 Delay V t OE# to Output GLQ R4 Delay V t RP# to Output ...
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... Sampled, but not 100% tested. 3. See Figure 8, “Read Operation Waveform” on page 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 input slew rate. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) 32 Mbit 90 ns 100 ns 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V Min Max ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 16. Read Operations — 64 Mbit Density # Sym R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 t OE# to Output Delay GLQV R5 t RP# to Output Delay PHQV R6 t CE# to Output in Low Z ...
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... Table 7, “Command Bus Operations” on page 24 3. Sampled, but not 100% tested. 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. 5. See Figure 9, “Write Operations Waveform” on page Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Density Product 3.0 V – 3 2.7 V – 3.6 V Note 4,5 4,5 ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 18. Write Operations—16 Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) Going PHWL W1 t Low PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / WLWH W3 WE# (CE#) Pulse Width t ELEH t / DVWH W4 Data Setup to WE# (CE#) Going High ...
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... Sampled, but not 100% tested. 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. 5. See Figure 9, “Write Operations Waveform” on page 6. V Max = 3.3 V for 32-Mbit 0.25 Micron product. CC Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Density Product 3.0 V – 3 2.7 V – 3 ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 20. Write Operations—64Mbit Density # Sym t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / WLWH W3 WE# (CE#) Pulse Width t ELEH t / DVWH W4 Data Setup to WE# (CE#) Going High t DVEH t / AVWH ...
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... EHQV3 Erase Time Program Suspend Latency WHRH1 EHRH1 Erase Suspend Latency WHRH2 EHRH2 NOTES: 1. Typical values measured Excludes external system-level overhead. 3. Sampled, but not 100% tested. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3 W10 V PP Parameter Note 1,3 1,3 = +25 °C and nominal voltages. ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 8.4 Reset Specifications Table 22. Reset Specifications Symbol RP# Low to Reset during Read t (If RP# is tied to V PLPH applicable) t RP# Low to Reset during Block Erase PLRH1 t RP# Low to Reset during Program PLRH2 NOTES < 100 ns the device may still reset but this is not guaranteed. ...
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... NOTE: C includes jig capacitance. L 8.6 Device Capacitance ° MHz A Symbol Output Capacitance OUT § Sampled, not 100% tested. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3 CCQ /2. Input rise and fall times (10% to 90%) < 5 ns. CCQ = V Min Device Under Test (pF § ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix A Write State Machine States This table shows the command state transitions based on incoming commands. Data Read Array Current State SR.7 When (FFH) Read Read Array “1” Array Read Array Read Status “1” ...
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... Erase Suspend Query Read Config. Read Query Ers.(Done) Read Config. Read Query Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Command Input (and Next State) Lock Setup Prot. Prog. Lock Confirm (60H) Setup (C0H) (01H) Lock Setup Prot. Prog. Setup Lock Setup Prot ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix B Flow Charts Figure 13. Word Program Flowchart Start Write 0x40, Word Address Write Data, Word Address Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status Register 1 SR[ SR[ SR[ Program Successful 52 WORD PROGRAM PROCEDURE ...
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... Array) Read Array Data Done No Reading Yes Write 0xD0 (Program Resume) Any Address Program Resumed Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) PROGRAM SUSPEND / RESUME PROCEDURE Bus Operation Command Read Write Status Program Write Suspend Read None Idle None Idle ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 15. Erase Suspend / Resume Flowchart Start Write 0xB0, Any Address Write 0x70, Any Address Read Status Register SR[7] = SR[6] = Write 0xFF Read Array (Read Array) Data Done Reading Write 0xD0, (Erase Resume) Any Address ...
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... SR[ 1,1 SR[4, SR[ SR[ Block Erase Successful Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) BLOCK ERASE PROCEDURE Bus Operation Command Write Write Read Suspend Erase Loop Idle No Suspend Yes Erase Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 17. Locking Operations Flowchart Start Write 0x60, Block Address Write either 0x01/0xD0/0x2F, Block Address Write 0x90 Read Block Lock Status Locking Change? Yes Write 0xFF Any Address Lock Change Complete 56 LOCKING OPERATIONS PROCEDURE Bus ...
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... Register Data SR[3], SR[ SR[3], SR[ SR[3], SR[ Program Successful Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) PROTECTION REGISTER PROGRAMMING PROCEDURE Bus Operation Write (Program Setup) Write (Confirm Data) Read Idle Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix C Common Flash Interface This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component ...
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... Block Erase Status (BSR[1]) allows system software to determine the success of the last block erase operation. BSR[1] can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) P_IDHI ID # PLO PrVendor PHI ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 27. Block Status Register Offset Length 1 0x(BA+2) 1 NOTES Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word). C.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...
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... Erase Block Region 2 Information bits 0– y+1 = number of identical-size erase blocks 0x2D 14 bits 16– region erase block(s) size are z x 256 bytes Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Description n µs n µ ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 31. Device Geometry Details 16 Mbit Address -B 0x27 --15 0x28 --01 0x29 --00 0x2A --00 0x2B --00 0x2C --02 0x2D --07 0x2E --00 0x2F --20 0x30 --00 0x31 --1E 0x32 --00 0x33 --00 0x34 --01 C.6 Intel-Specific Extended Query Table Certain flash features and commands are optional. The Intel - Specific Extended Query table specifies this and other similar types of information ...
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... Lock/bytes JEDEC -plane physical high address bits 16–23 = “n” such that 2 bits 24–31 = “n” such that 2 0x(P+13) Reserved for future use NOTES: 1. The variable pointer which is defined at CFI offset 0x15. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Description Address 3E: 3F: 40: 41: 42: Description n ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix D Mechanical Specifications Figure 19. BGA* and VF BGA Package Drawing & Dimensions Ball A1 Corner Top View - Bump Side down Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length 8M (.25) Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13) Package Body Length 64M ( ...
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... If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. 4. Pin 1 will always supersede above pin one notes. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) See Notes and ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 21. Easy BGA Package Drawing & Dimension Ball A1 Corner Top View - Ball side down A1 A2 Dimensions Table Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Document/Tool 3 Volt Advanced+ Boot Block Flash Memory Specification Update AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture ® Intel Flash Data Integrator (FDI) Software Developer’s Kit ® ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix F Ordering Information Figure 22. Component Ordering Information Package TE = 48-Lead TSOP GT = 48-Ball µBGA* CSP BGA CSP RC = Easy BGA Product line designator ® for all Intel Flash products Device Density 640 = x16 (64 Mbit) 320 = x16 (32 Mbit) ...