CY7C1360B-166AC Cypress Semiconductor Corp, CY7C1360B-166AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1360B-166AC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1360B-166AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1542

Document #: 38-05291 Rev. *C
CY7C1360B–Pin Definitions
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
0
Name
, A
1
2
3
A,
C,
[2]
1
BW
BW
, A
B
D
82,99,100
37,36,32,
33,34,35,
43,44,45,
46,47,48,
49,50,81,
93,94,95,
Enable
3-Chip
TQFP
96
88
87
89
98
97
92
86
83
92,99,100
37,36,32,
33,34,35,
44,45,46,
47,48,49,
50,81,82,
93,94,95,
Enable
2-Chip
TQFP
96
88
87
89
98
97
86
83
-
T3,T4,A5,
T5,A6,B6,
P4,N4,
A2,C2,
R2,3A,
B3,C3,
B5,C5,
L5,G5,
C6,R6
G3,L3
BGA
M4
H4
G4
K4
E4
B2
F4
-
R8,R9,R10,
B10,P3,P4,
P8,P9,P10,
P11,R3,R4,
R6,P6,A2,
B5,A5,A4,
A10,B2,
fBGA
R11
B4
B7
A7
B6
A3
B3
A6
B8
A9
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchro-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
nous
I/O
Address Inputs used to select one of the 256K
address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
CE
to the two-bit counter. .
Byte Write Select Inputs, active LOW. Qualified
with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written,
regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled
on the rising edge of CLK. This signal must be as-
serted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
and CE
ignored if CE
Chip Enable 2 Input, active HIGH. Sampled on
the rising edge of CLK. Used in conjunction with
CE
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
and CE
for AJ package version. Not connected for BGA.
Where referenced, CE
throughout this document for BGA.
Output Enable, asynchronous input, active
LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the first
clock of a read cycle when emerging from a
deselected state.
Advance Input signal, sampled on the rising
edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
2
1
, and CE
and CE
2
3
[2]
to select/deselect the device. Not available
to select/deselect the device. ADSP is
3
3
1
[2]
[2]
is HIGH.
are sampled active. A
to select/deselect the device.
Description
3
[2]
is assumed active
CY7C1360B
CY7C1362B
X
and BWE).
1
Page 6 of 34
, A
0
are fed
2
1
1
,