CY7C1327F-133AC Cypress Semiconductor Corp, CY7C1327F-133AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1327F-133AC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1327F-133AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (256K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1536

Document #: 38-05216 Rev. *B
Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1327F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
V
V
V
MODE
NC
DD
SS
DDQ
1
Name
is HIGH.
15,41,65,
21,26,40,
55,60,67,
27,54,61,
1,2,3,6,7,
14,16,25,
28,29,30,
38,39,42,
43,51,52,
53,56,57,
66,75,78,
71,76,90
79,95,96
5,10,17,
4,11,20,
TQFP
70,77
91
31
(continued)
M3,N3,P3,
G5,H5,K5,
M1,U1,A7,
U5,E6,G6,
K6,M6,P6,
B1,C1,E1,
G1,K1,P1,
R1,T1,D2,
U6,B7,C7,
D3,E3,F3,
H3,K3,L3,
D5,E5,F5,
M5,N5,P5
F7,J7,M7,
F2,H2,L2,
N2,U2,J3,
U3,D4,L4,
D7,H7,L7,
N7,R5,R7
A1,F1,J1,
T4,U4,J5,
J2,C4,J4,
R4,J6
BGA
U7
R3
[A:B]
) inputs. A Global Write
Power Supply Power supply inputs to the core of the device.
1
I/O Ground
, CE
Ground
Input-
Static
I/O
2
, CE
3
) and an
Ground for the device.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence.
When tied to V
is a strap pin and should remain static during device operation. Mode Pin
has an internal pull-up.
No Connects. Not internally connected to the die
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single Read cycles are supported. Once the SRAM is
deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output will three-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
DD
1
1
, CE
is HIGH. The address presented to the address inputs (A)
or left floating selects interleaved burst sequence. This
1
, CE
2
, CE
2
, CE
3
are all asserted active, and (3) the Write
Description
3
are all asserted active. The address
CY7C1327F
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[A:B]
) and