CY7C1361B-100AC Cypress Semiconductor Corp, CY7C1361B-100AC Datasheet - Page 14

• Manufacturer Part Number: CY7C1361B-100AC
• Description: IC SRAM 9MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1504

Document #: 38-05302 Rev. *B
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
3
DDZZ
ZZS
ZZREC
ZZI
RZZI
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
Parameter
the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't
care for the remainder of the write cycle.
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Cycle Description
[ 3, 4, 5, 6, 7]
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
Address
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Description
Used
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
H
H
H
X
X
X
X
X
H
X
X
H
X
H
L
L
L
L
L
L
L
L
1
CE
H
H
H
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
CE
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
3
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ADSP
Test Conditions
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
DD
DD
– 0.2V
– 0.2V
ADSC
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
ADV WRITE OE CLK
X
. Writes may occur only on subsequent clocks after
X
X
X
X
X
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
H
H
2t
X
X
X
X
X
X
X
L
L
L
L
L
Min.
CYC
0
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CY7C1361B
CY7C1363B
2t
2t
Max.
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
35
X
CYC
CYC
Page 14 of 34
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
DQ
Q
Q
Q
Q
Q
Q
Unit
D
D
D
D
D
mA
ns
ns
ns
ns