CY7C09189-9AC Cypress Semiconductor Corp, CY7C09189-9AC Datasheet

IC SRAM 576KBIT 67MHZ 100LQFP

CY7C09189-9AC

Manufacturer Part Number
CY7C09189-9AC
Description
IC SRAM 576KBIT 67MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C09189-9AC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
576K (64K x 9)
Speed
67MHz
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1180

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C09189-9AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cypress Semiconductor Corporation
Document #: 38-06039 Rev. *A
Features
Notes:
1.
2.
3.
• True dual-ported memory cells which allow simulta-
• Six Flow-Through/Pipelined devices
• Three Modes
• Pipelined output mode on both ports allows fast 100-
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5
Logic Block Diagram
R/W
OE
CE
CE
FT/Pipe
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
MHz cycle time
(max.)
— 64K x 8/9 organizations (CY7C09089/189)
— 128K x 8/9 organizations (CY7C09099/199)
— Flow-Through
— Pipelined
— Burst
0
See page 7 for Load Conditions.
I/O
A
–A
0L
1L
0L
0
L
–A
0
L
L
L
–I/O
–I/O
[3]
15/16L
15
L
L
for 64K; and A
7
[2]
L
7/8L
for x8 devices; I/O
16/17
0
–A
For the most recent information, visit the Cypress web site at www.cypress.com
16
0
for 128K devices.
–I/O
8/9
0/1
0/1
1
0
1
Counter/
Register
Address
8
Decode
for x9 devices.
0
[1]
/7.5/9/12 ns
3901 North First Street
Control
I/O
True Dual-Ported
Synchronous Dual-Port Static RAM
RAM Array
• Low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70908
and IDT709089
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
San Jose
0
Counter/
Address
Register
Decode
CA 95134
0/1
1
1
0
0/1
64K/128K x 8/9
8/9
Revised December 27, 2002
CY7C09089/99
CY7C09189/99
16/17
I/O
408-943-2600
A
CNTRST
0R
0
FT/Pipe
CNTEN
–A
–I/O
ADS
15/16R
R/W
[3]
CLK
CE
CE
OE
[2]
7/8R
0R
1R
R
R
R
R
R
R
R

Related parts for CY7C09189-9AC

CY7C09189-9AC Summary of contents

Page 1

... Available in 100-pin TQFP • Pin-compatible and functionally equivalent to IDT70908 and IDT709089 [1] /7.5/9/ I/O I/O Control Control True Dual-Ported RAM Array • 3901 North First Street • CY7C09089/99 CY7C09189/99 64K/128K 0/1 8/9 I/O 16/17 Counter/ Address Register Decode San Jose • ...

Page 2

... Functional Description The CY7C09089/99 and CY7C09189/99 are high-speed syn- chronous CMOS 64K and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, and data lines allow for minimal set- up and hold times ...

Page 3

... For CY7C09089, pin #23 connected to V through device. Document #: 38-06039 Rev. *A 100-Pin TQFP (Top View CY7C09099 (128K x 8) CY7C09089 (64K equivalent to an IDT x8 pipelined device; connecting pin #23 and #53 to GND is equivalent to an IDT x8 flow- CC CY7C09089/99 CY7C09189/ A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R 65 A15R 64 ...

Page 4

... Pipelined) Typical Operating Current I (mA) CC Typical Standby Current for I (mA) SB1 (Both ports TTL Level) Typical Standby Current for I (mA) SB3 (Both ports CMOS Level) Note: 7. This pin is NC for CY7C09189. Document #: 38-06039 Rev. *A 100-Pin TQFP (Top View CY7C09199 (128K x 9) ...

Page 5

... IH –I/O for x8 devices; I/O –I Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current...................................................... >200mA Operating Range Range Commercial [9] Industrial CY7C09089/99 CY7C09189/99 AND CE must be asserted MAX for x9 devices). 8 Ambient Temperature V CC 0°C to +70°C 5V 10% 40°C to +85°C ...

Page 6

... Com’l. 0.05 0.5 0.05 [9] Ind. Com’l. 160 200 145 [9] Ind. Description Test Conditions T = 25° MHz 5.0V CC AND CE 0 CY7C09089/99 CY7C09189/99 CY7C09089/99 CY7C09189/99 -9 -12 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0 420 210 350 195 245 410 105 110 ...

Page 7

... Note: 11. Test Conditions pF. Document #: 38-06039 Rev 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) [11] 3.0V GND = 1. Capacitance (pF) (b) Load Derating Curve CY7C09089/99 CY7C09189/99 5V OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for CKLZ OLZ including scope and jig) ALL INPUT PULSES 90% 90% 10% 10 ...

Page 8

... Test conditions used are Load 2. 13. This parameter is guaranteed by design, but is not production tested. Document #: 38-06039 Rev. *A CY7C09089/99 CY7C09189/99 [ Min. Max. Min. Max. Min 100 6.5 7.5 12 6 6.5 7 CY7C09089/99 CY7C09189/99 -12 Max. Min. Max. Unit 40 33 MHz 67 50 MHz Page ...

Page 9

... Q n [14, 15, 16, 17 CYC2 t CL2 A A n+1 t CD2 Q t CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09089/99 CY7C09189/ n+2 n+3 t CKHZ Q Q n+1 n OHZ OLZ n+2 ...

Page 10

... CWDD Document #: 38-06039 Rev. *A CL2 CD2 HC CD2 [20, 21, 22, 23 MATCH CD1 CWDD . for the left port, which is being written to. IH CY7C09089/99 CY7C09189/ CD2 CKHZ CKLZ CD2 CKHZ CKLZ NO NO MATCH t CD1 VALID >maximum specified, then data is not CWDD CCS CKHZ CD2 D ...

Page 11

... During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06039 Rev. *A [17, 24, 25, 26 n+1 n CD2 CKHZ Q n READ NO OPERATION [17, 24, 25, 26 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09089/99 CY7C09189/ n+3 n CKLZ WRITE READ A A n+4 n CKLZ CD2 READ Page CD2 Q n+3 Q n+4 ...

Page 12

... OUT OE Document #: 38-06039 Rev. *A [15, 18, 24, 25 n+1 n CD1 CKHZ NO READ OPERATION [15, 18, 24, 25 n OHZ READ CY7C09089/99 CY7C09189/ n+2 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n CD1 CKLZ WRITE READ A n+4 t CD1 A n+5 t CD1 n+4 Page ...

Page 13

... R/W and CNTRST = Document #: 38-06039 Rev. *A [27] t SAD t SCN t CD2 READ WITH COUNTER [27 n+1 READ WITH COUNTER . IH CY7C09089/99 CY7C09189/99 t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+2 READ COUNTER HOLD WITH COUNTER Q n+3 Q n+3 Page ...

Page 14

... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06039 Rev n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09089/99 CY7C09189/99 [28, 29 n+2 n n+2 n+3 WRITE WITH COUNTER . IH A n+4 n+4 ...

Page 15

... HRST CNTRST t SD DATA IN DATA OUT COUNTER RESET Notes: 30 31. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06039 Rev. *A [17, 24, 30, 31 WRITE READ ADDRESS 0 ADDRESS 0 CY7C09089/99 CY7C09189/ n READ READ ADDRESS 1 ADDRESS n Page n ...

Page 16

... I/O Mode Reset out( out( out( Increment out(n+ CY7C09089/99 CY7C09189/99 –I/O Operation 8 [35] Deselected [35] Deselected Write IN [33] Read Outputs Disabled Operation Counter Reset to Address 0 Load Address Load into Counter Hold External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page ...

Page 17

... Ordering Code 6.5 CY7C09099-6AC 7.5 CY7C09099-7AC 9 CY7C09099-9AC CY7C09099-9AI 12 CY7C09099-12AC 64K x9 Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09189-6AC 7.5 CY7C09189-7AC 9 CY7C09189-9AC 12 CY7C09189-12AC 128K x9 Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09199-6AC 7.5 CY7C09199-7AC 9 CY7C09199-9AC CY7C09199-9AI 12 CY7C09199-12AC Document #: 38-06039 Rev. *A Package Name ...

Page 18

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C09089/99 CY7C09189/99 51-85048-B Page ...

Page 19

... Document Title: CY7C09089/99, CY7C09189/99 64K/128K x 8/9 Synchronous Dual Port Static RAM Document Number: 38-06039 Issue REV. ECN NO. Date ** 110187 10/21/01 *A 122289 12/27/02 Document #: 38-06039 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00663 to 38-06039 RBI Added power up information to maximum ratings information. ...

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