CY7C0251-15AC Cypress Semiconductor Corp, CY7C0251-15AC Datasheet
CY7C0251-15AC
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CY7C0251-15AC Summary of contents
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... Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • organization (CY7C024) • organization (CY7C0241) • organization (CY7C025) • organization (CY7C0251) • 0.65-micron CMOS for optimum speed/power • High-speed access • Low operating power 150 mA (typ.) CC • ...
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... A 0L R/W L SEM L INT L Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. I/O –I/O on the CY7C0241/0251 I/O –I/O on the CY7C0241/0251 Document #: 38-06035 Rev. ** I/O I/O CONTROL CONTROL MEMORY ADDRESS ARRAY DECODER INTERRUPT CE SEMAPHORE L ARBITRATION M/S CY7C024/0241 CY7C025/0251 R [3] – ...
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Pin Configurations I I I/O 10L 15 I/O 11L I/O 16 12L 17 I/O 13L 18 GND I/O 19 14L 20 I/O 15L GND ...
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Pin Configurations (continued) 100 I I/O 4 17L I/O 11L 5 I/O 6 12L I/O 13L 7 I/O 14L 8 GND 9 I/O 10 15L I/O 11 16L GND ...
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Selection Guide Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I (mA) SB1 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................– +150 C ...
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Electrical Characteristics Over the Operating Range (continued) Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current IX I Output Leakage Current Output Disabled, ...
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Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From OHA Address Change [10 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description [15] BUSY TIMING t BUSY LOW from Address BLA Match t BUSY HIGH from Address BHA Mismatch t BUSY LOW from CE LOW BLC t BUSY HIGH from CE HIGH BHC t ...
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Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS t OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT I CC CURRENT I SB [18, ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [27,28 R/W NOTE 30 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [27,28 R/W DATA IN Notes: 23. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS 0 2 SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A – ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE ValidFirst: R ADDRESS L BUSY L Busy Timing Diagram No.2 (Address Arbitration) Left Address ...
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Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFF (1FFF CY7C025 R/W L INT R [39] t INS Right Side Clears INT : R ADDRESS R ...
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... RAM cells, I/O and address lines, and control sig- nals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port commu- nication ...
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Table 1. Non-Contending Read/Write Inputs CE R ...
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Ordering Information 4K x16 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C024–15AC CY7C024–15JC 25 CY7C024–25AC CY7C024–25JC CY7C024–25AI CY7C024–25JI 35 CY7C024–35AC CY7C024–35JC CY7C024–35AI CY7C024–35JI 55 CY7C024–55AC CY7C024–55JC CY7C024–55AI CY7C024–55JI Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C025–15AC CY7C025–15JC ...
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... Ordering Code 15 CY7C0251–15AC 25 CY7C0251–25AC CY7C0251–25AI 35 CY7C0251–35AC CY7C0251–35AI 55 CY7C0251–55AC CY7C0251–55AI Document #: 38-06035 Rev. ** Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...
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... Document #: 38-06035 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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Document Title: CY7C024/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06035 Issue REV. ECN NO. Date ** 110177 09/29/01 Document #: 38-06035 Rev. ** Orig. of Change Description of Change ...