CY7C1021B-15VC Cypress Semiconductor Corp, CY7C1021B-15VC Datasheet - Page 4
![IC SRAM 1MBIT 15NS 44SOJ](/photos/7/23/72391/428-44-soj_sml.jpg)
CY7C1021B-15VC
Manufacturer Part Number
CY7C1021B-15VC
Description
IC SRAM 1MBIT 15NS 44SOJ
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1021B-12VC.pdf
(11 pages)
Specifications of CY7C1021B-15VC
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
1M (64K x 16)
Speed
15ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
44-SOJ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1010
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1021B-15VC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Characteristics
Document #: 38-05145 Rev. **
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Notes:
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
1.
2.
3.
4.
5.
6.
7.
8.
Parameter
V
T
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect these parameters.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
At any given temperature and voltage condition, t
t
The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
OL
HZOE
A
IL
is the “Instant On” case temperature.
/I
(min.) = –2.0V for pulse durations of less than 20 ns.
OH
, t
HZBE
and 30-pF load capacitance.
, t
HZCE
[8]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
Description
[5]
[6]
Over the Operating Range
[6]
[6, 7]
[6]
[6, 7]
[6, 7]
HZCE
is less than t
LZCE
, t
Min.
HZOE
7C10211B-10
10
10
3
0
3
0
0
8
7
0
0
7
5
0
3
7
is less than t
Max.
10
10
10
5
5
5
5
5
5
LZOE
, and t
Min.
HZWE
7C1021B-12
12
12
3
0
3
0
0
9
8
0
0
8
6
0
3
8
is less than t
Max.
12
12
12
6
6
6
6
6
6
LZWE
for any given device.
Min.
7C1021B-15
15
15
10
10
10
CY7C10211B
3
0
3
0
0
0
0
8
0
3
9
CY7C1021B/
Max.
15
15
15
7
7
7
7
7
7
Page 4 of 11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns