MT41J512M8THU-187E:A Micron Technology Inc, MT41J512M8THU-187E:A Datasheet - Page 123
MT41J512M8THU-187E:A
Manufacturer Part Number
MT41J512M8THU-187E:A
Description
IC DDR3 SDRAM 4GBIT 82FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT41J256M8JE-187EA.pdf
(181 pages)
Specifications of MT41J512M8THU-187E:A
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
4G (512M x 8)
Speed
533MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
82-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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MPR Register Address Definitions and Bursting Order
Table 73:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
MR3[2]
1
1
1
1
MPR Readouts and Burst Order Bit Mapping
MR3[1:0]
00
01
10
11
Notes:
pattern for system
READ predefined
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0
• A13 is a “Don’t Care”
• BA[2:0] are a “Don’t Care”
The MPR currently supports a single data format. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating 0–1 bit
pattern.
Examples of the different types of predefined READ pattern bursts are shown in
Figure 59 on page 124, Figure 60 on page 125, Figure 61 on page 126, and Figure 62 on
page 127.
1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected
calibration
MPR agent.
Function
RFU
RFU
RFU
Length
Burst
BL8
BC4
BC4
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
123
A[2:0]
Read
000
000
100
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
2Gb: x4, x8, x16 DDR3 SDRAM
Burst Order and Data Pattern
Burst order: 0, 1, 2, 3, 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1
Predefined pattern: 0, 1, 0, 1
Burst order: 0, 1, 2, 3
Burst order: 4, 5, 6, 7
©2006 Micron Technology, Inc. All rights reserved.
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