MT41J512M8THU-15E:A Micron Technology Inc, MT41J512M8THU-15E:A Datasheet - Page 137
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MT41J512M8THU-15E:A
Manufacturer Part Number
MT41J512M8THU-15E:A
Description
IC DDR3 SDRAM 4GBIT 82FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT41J256M8JE-187EA.pdf
(181 pages)
Specifications of MT41J512M8THU-15E:A
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
4G (512M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
82-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DDR3_D4.fm - Rev G 2/09 EN
A DQS to DQ output timing is shown in Figure 76 on page 138. The DQ transitions
between valid data outputs must be within
DQS must also maintain a minimum HIGH and LOW time of
READ preamble, the DQ balls will either be floating or terminated depending on the
status of the ODT signal.
Figure 77 on page 139 shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±
out has no timing relationship to clock, only to DQS, as shown in Figure 77 on page 139.
Figure 77 on page 139 also shows the READ preamble and postamble. Normally, both
DQS and DQS# are High-Z to save power (V
DQS is driven LOW and DQS# is HIGH for
The READ postamble,
During the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete,
the DQ will either be disabled or will continue terminating depending on the state of the
ODT signal. Figure 82 on page 142 demonstrates how to measure
t
RPST, is one half clock from the last DQS, DQS# transition.
137
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
DQSCK of the clock crossing point. The data
RPRE. This is known as the READ preamble.
t
DD
DQSQ of the crossing point of DQS, DQS#.
Q). Prior to data output from the DRAM,
2Gb: x4, x8, x16 DDR3 SDRAM
t
QSH and
©2006 Micron Technology, Inc. All rights reserved.
t
RPST.
t
QSL. Prior to the
Operations
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