MT45V256KW16PEGA-70 WT TR Micron Technology Inc, MT45V256KW16PEGA-70 WT TR Datasheet - Page 5

• Manufacturer Part Number: MT45V256KW16PEGA-70 WT TR
• Description: IC PSRAM 4MBIT 70NS 48VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45V256KW16PEGA-70 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 4M (256K x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 48-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1416-1

General Description
Functional Block Diagram
Figure 2:
PDF: 09005aef832450a3/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN
Functional Block Diagram 256K x 16
Notes:
Micron
power, portable applications. The MT45V256KW16PE is a 4Mb DRAM core device orga-
nized as 256K x 16 bits. These devices include the industry-standard, asynchronous
memory interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on an asynchronous memory bus, PSRAM products incorporate
a transparent self refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
A user-accessible configuration register (CR) defines how the PSRAM device performs
on-chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power-up and can be updated at any
time during normal operation.
Special attention has been focused on current consumption during self refresh. This
product includes two system-accessible mechanisms to minimize refresh current.
Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array
refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts refresh operation altogether and is
used when no vital information is stored in the device. The system-configurable refresh
mechanisms are accessed through the CR.
WE #
1. Functional block diagrams illustrate simplified device operation. See the ball description
OE #
UB #
CE #
LB #
ZZ #
table, bus operations table, and timing diagrams for detailed information.
A[17:0]
®
PSRAM products are high-speed, CMOS memory devices developed for low-
Control
logic
4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16
Address decode
Configuration
register (CR)
5
logic
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256K x 16
memory
DRAM
array
General Description
©2007 Micron Technology, Inc. All rights reserved.
buffers
output
Input/
MUX
and
DQ[7:0]
DQ[15:8]