MT48H16M32LFCM-75:A TR Micron Technology Inc, MT48H16M32LFCM-75:A TR Datasheet - Page 32
![IC SDRAM 512MBIT 133MHZ 90VFBGA](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48H16M32LFCM-75:A TR
Manufacturer Part Number
MT48H16M32LFCM-75:A TR
Description
IC SDRAM 512MBIT 133MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT48H16M32LFCM-75_ITA_TR.pdf
(73 pages)
Specifications of MT48H16M32LFCM-75:A TR
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
512M (16M x 32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1330-2
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Figure 21:
Figure 22:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
Random WRITE Cycles
WRITE-to-READ
Notes:
Notes:
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same opera-
tion that would result from the same fixed-length burst with auto precharge. The disad-
vantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
COMMAND
1. Each WRITE command may be to any bank. DQM is LOW.
COMMAND
1. The WRITE command may be to any bank, and the READ command may be to any bank.
ADDRESS
ADDRESS
DQM is LOW. CL = 2 for illustration.
CLK
CLK
DQ
DQ
WRITE
BANK,
BANK,
COL n
WRITE
COL n
D
T0
D
T0
n
IN
n
IN
WRITE
BANK,
n + 1
COL a
NOP
T1
D
T1
D
IN
a
IN
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
BANK,
WRITE
COL x
BANK,
COL b
READ
T2
D
T2
x
IN
32
DON’T CARE
WRITE
BANK,
COL m
T3
T3
NOP
D
m
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
D
T4
OUT
b
DON’T CARE
NOP
b + 1
T5
D
OUT
©2005 Micron Technology, Inc. All rights reserved.
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