MT46H8M16LFCF-75 IT TR Micron Technology Inc, MT46H8M16LFCF-75 IT TR Datasheet - Page 48

• Manufacturer Part Number: MT46H8M16LFCF-75 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-75 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1277-1

Table 13:
Table 14:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
Parameter
Parameter/Condition
Delta input/output capacitance: DQs, DQS, DM
Delta input capacitance: Command and address
Delta input capacitance: CK, CK#
Input/output capacitance: DQs, DQS, DM
Input capacitance: Address
Input capacitance: Command
Input capacitance: CK, CK#
Operating one bank active precharge current:
t
Address inputs are switching every two clock cycles; Data bus inputs
are stable
Precharge power-down standby current: All banks idle; CKE is LOW; CS
is HIGH;
every two clock cycles; Data bus inputs are stable
Precharge power-down standby current with clock stopped: All banks
idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and
control inputs are switching every two clock cycles; Data bus inputs
are stable
Precharge non power-down standby current: All banks idle;
CKE = HIGH; CS = HIGH;
are switching every two clock cycles; Data bus inputs are stable
Precharge non power-down standby current: Clock stopped; All banks
idle; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH Address and
control inputs are switching every two clock cycles; Data bus inputs
are stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH;
every two clock cycles; Data bus inputs are stable
Active power-down standby current: Clock stopped; One bank active;
CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and control
inputs are switching every two clock cycles; Data bus inputs are stable
Active non power-down standby: One bank active; CKE = HIGH;
CS = HIGH;
every two cycles; Data bus inputs are stable
Active non-power-down standby: Clock stopped; One bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control
inputs are switching every two clock cycles; Data bus inputs are stable
Operating burst read: One bank active; BL = 4;
Continuous read bursts; I
50% data changing each burst
Operating burst write: One bank active; BL = 4;
Continuous WRITE bursts; Address inputs are switching; 50 percent
data changing each burst
CK =
t
CK (MIN); CKE is HIGH; CS is HIGH between valid commands;
t
CK =
t
t
CK =
CK =
Capacitance
Notes: 13; notes appear on pages 52–54
I
Notes: 1–5, 7, 10, 12, 14 notes appear on pages 52–54; V
t
DD
CK (MIN); Address and control inputs are switching
t
t
CK (MIN); Address and control inputs are switching
CK (MIN); Address and control inputs are switching
Specifications and Conditions
t
CK =
OUT
= 0mA; Address inputs are switching;
t
CK (MIN); Address and control inputs
t
t
RC =
CK =
t
CK =
t
RC (MIN);
t
CK (MIN);
t
CK (MIN);
48
Symbol
CDCK
CDIO
CCK
CIO
CDI
CI
CI
128Mb: 8 Meg x 16 Mobile DDR SDRAM
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = +1.8V ±0.1V, V
Symbol
I
I
I
I
I
I
I
I
DD
I
DD
I
DD
DD
DD
DD
DD
DD
I
DD
DD
DD
Min
3.0
1.5
1.5
1.5
2NS
3NS
2PS
3PS
4W
–
–
–
2N
3N
4R
2P
3P
0
-75
200
200
80
25
15
25
20
95
95
3
3
Max
1.00
1.75
0.25
Max
5.5
4.0
5.0
4.5
Electrical Specifications
DD
200
200
= +1.8V ±0.1V
-10
75
25
15
25
20
90
90
3
3
©2004 Micron Technology, Inc. All rights reserved.
Units
pF
pF
pF
pF
pF
pF
pF
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
Notes
Notes
20, 28
20, 28
20, 28
20, 28
21
26
26
19
34
34
19
19
19
19