MT47H256M4BT-5E:A TR Micron Technology Inc, MT47H256M4BT-5E:A TR Datasheet - Page 27
![IC DDR2 SDRAM 1GBIT 5NS 92FBGA](/photos/7/26/72643/557-92-fbga_sml.jpg)
MT47H256M4BT-5E:A TR
Manufacturer Part Number
MT47H256M4BT-5E:A TR
Description
IC DDR2 SDRAM 1GBIT 5NS 92FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H256M4HQ-5EE_TR.pdf
(131 pages)
Specifications of MT47H256M4BT-5E:A TR
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (256M x 4)
Speed
5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
92-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1206-1
- Current page: 27 of 131
- Download datasheet (10Mb)
I
Table 9: I
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Timing patterns for 8-bank x4/x8 devices
Timing patterns for 8-bank x16 devices
DD7
Speed
Grade
-187E
-187E
-37E
-25E
-37E
-25E
-5E
-3E
-25
-5E
-3E
-25
-3
-3
Conditions
DD7
I
A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D D
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D
D D D A7 RA7 D D D D
DD7
Timing Patterns (8-Bank Interleave READ Operation)
Timing Patterns
Notes:
The detailed timings are shown below for I
Table 8 (page 26) conflict with pattern requirements of Table 9, then Table 9 require-
ments take precedence.
1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at
3. Control and address bus inputs are stable during deselects.
27
Electrical Specifications – I
t
RC (I
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD
DD7
) without violating
. Where general I
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.
t
DD
RRD (I
parameters in
DD
DD
) using a BL = 4.
Parameters
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