MT28F400B5WP-8 TET Micron Technology Inc, MT28F400B5WP-8 TET Datasheet
![IC FLASH 4MBIT 80NS 48TSOP](/photos/7/22/72295/557-48-tsop_sml.jpg)
MT28F400B5WP-8 TET
Specifications of MT28F400B5WP-8 TET
Related parts for MT28F400B5WP-8 TET
MT28F400B5WP-8 TET Summary of contents
Page 1
... Contact factory for availability. Part Number Example: MT28F400B5WG-8 T 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. SMART 5 BOOT BLOCK FLASH MEMORY MT28F004B5 MT28F400B5 5V Only, Dual Supply (Smart 5) 0.18µm Process Technology 40-Pin TSOP Type I ...
Page 2
... Order Number and Part Marking MT28F400B5WG-8 B MT28F400B5WP-8 B MT28F400B5WG-8 T MT28F400B5WP-8 T MT28F400B5WG-8 BET MT28F400B5WP-8 BET MT28F400B5WG-8 TET MT28F400B5WP-8 TET MT28F004B5VG-8 B MT28F004B5VG-8 T MT28F400B5SG-8 BET MT28F004B5VG-8 TET Notes: 1. Contact factory for availability. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY Pin Assignment (Top View) ...
Page 3
... Command OE# Execution WE# Logic RP Notes: 1. Does not apply to MT28F004B5. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY Functional Block Diagram 16KB Boot Block 8KB Parameter Block 18 (19) 9 8KB Parameter Block 96KB Main Block 9 (10) 128KB Main Block Addr. Counter 128KB Main Block ...
Page 4
... SYMBOL TYPE WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL the memory array. WP# Input Write Protect: Unlocks the boot block when HIGH and RP WRITE or ERASE operation on other blocks. ...
Page 5
... Operation must be preceded by WRITE SETUP command. 5. The READ ARRAY command must be issued before reading the array after writing or erasing. 6. When WP RP# may A1–A8, A10–A17 = Value reflects DQ8–DQ15. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY 1 CE# OE# WE# WP# BYTE ...
Page 6
... Operation must be preceded by ERASE SETUP command. 4. Operation must be preceded by WRITE SETUP command. 5. The READ ARRAY command must be issued before reading the array after writing or erasing. 6. When WP RP# may A1–A8, A10–A18 = 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY 1 RP# CE# OE# WE ...
Page 7
... The MT28F400B5 allows selection of an 8-bit (512K 16-bit (256K x 16) data bus for reading and writ- ing the memory. The BYTE# pin is used to select the bus width. In the x16 configuration, control data is read or written only on the lower eight bits (DQ0– ...
Page 8
... Command Execution Logic (CEL) The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, ID register or status register). Commands may be issued to the CEL while the ISM is active. However, there are restric- tions on what commands are allowed in this condition ...
Page 9
... Parameter Block 02000h 04000h 01FFFh 03FFFh 16KB Boot Block 00000h 00000h 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY Figure 1 Memory Address Maps MT28F004B5/400B5xx-xxT WORD ADDRESS 3FFFFh 3E000h 3DFFFh 3D000h 3CFFFh 3C000h 3BFFFh 30000h 2FFFFh ...
Page 10
... The MT28F400B5 features selectable bus widths. When the memory array is accessed as a 256K x 16, BYTE# is HIGH, and data will be output on DQ0– DQ15. To access the memory array as a 512K x 8, BYTE# must be LOW, DQ8–DQ14 are High-Z, and all data is output on DQ0–DQ7. The DQ15/( pin becomes the lowest order address input so that 524,288 locations can be read ...
Page 11
... Memory Array A WRITE to the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. Setting any bits to a logic 1 requires that the entire block be erased. To perform a WRITE, OE# must be HIGH, CE# and WE# must be LOW, and V must be set to V ...
Page 12
... SR0-2 RESERVED 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY ISM. The erase, write and V cleared using CLEAR STATUS REGISTER. If the Vpp status bit (SR3) is set, the CEL does not allow further WRITE or ERASE operations until the status register is cleared ...
Page 13
... Addresses are “Don’t Care” in first cycle but must be held stable Address to be written Data to be written to WA. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY first cycle. The next cycle is the WRITE, during which the write address and data are issued and V brought to V ...
Page 14
... Notes: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY ERASE Suspension The only command that may be issued while an ERASE is in progress is ERASE SUSPEND. This com- mand enables other commands to be executed while pausing the ERASE in progress ...
Page 15
... WRITE or ERASE is completed. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY POWER-UP The likelihood of unwanted WRITE or ERASE opera- tions is minimized because two consecutive cycles are required to execute either operation. However, to reset ...
Page 16
... If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY Start (WRITE completed Micron Technology, Inc ...
Page 17
... If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY 1 Start (ERASE completed) NO YES ...
Page 18
... MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY ERASE SUSPEND/RESUME Sequence Start (ERASE in progress) WRITE B0h (ERASE SUSPEND STATUS REGISTER READ NO SR7 = 1? YES NO SR6 = 1? YES WRITE FFh (READ ARRAY) Done NO Reading? YES WRITE D0h (ERASE RESUME) Resume ERASE 18 ERASE Completed Micron Technology, Inc ...
Page 19
... OUT CC Notes: 1. All voltages referenced to V 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to ....-0.5V to +6V** SS the device. This is a stress rating only, and functional † ...
Page 20
... DEEP POWER-DOWN CURRENT Notes: 1. Vcc = MAX during Icc tests. 2. Icc is dependent on cycle rates. 3. Icc is dependent on output loading. Specified values are obtained with the outputs open. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY ≤ +70ºC) and Extended Temperature (-40ºC ≤ ...
Page 21
... RP# HIGH to output valid delay OE# or CE# HIGH to output in High-Z Output hold time from OE#, CE# or address change RP# LOW pulse width Notes: 1. OE# may be delayed by 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY ≤ +70ºC) and Extended Temperature (-40ºC ≤ SYMBOL ACE ...
Page 22
... Extended Temperature (-40ºC ≤ T ≤ +85ºC) A -8/-8 ET SYMBOL MIN ACE t AOE t AA Notes: 1. BYTE# = HIGH (MT28F400B5 only). 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY = 100pF L WORD-WIDE READ CYCLE VALID ADDRESS ACE t AOE MAX UNITS SYMBOL t ns RWH ...
Page 23
... Extended Temperature (-40ºC ≤ T -8/-8 ET SYMBOL MIN ACE t AOE t AA Notes: 1. BYTE# = LOW (MT28F400B5 only). 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY BYTE-WIDE READ CYCLE VALID ADDRESS ACE t AOE HIGH-Z t RWH ≤ +70ºC) A ≤ +85ºC) A MAX UNITS SYMBOL ...
Page 24
... Applies to MT28F004B5 and MT28F400B5 with BYTE = LOW. 6. Parameter is specified when device is not accessed. Actual current draw will READ is executed while the device is in erase suspend mode. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY 1 ≤ +70ºC) and Extended Temperature (-40ºC ≤ SYMBOL ...
Page 25
... REL is required to relock boot block after WRITE or ERASE to boot block. 6. Typical values measured Assumes no system overhead. 8. Typical WRITE times use checkerboard data pattern. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY ≤ +70ºC) and Extended Temperature (-40ºC ≤ SYMBOL t WC ...
Page 26
... Notes: 1. Address inputs are “Don’t Care” but must be held stable BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F400B5 only). 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY WRITE/ERASE CYCLE WE#-CONTROLLED WRITE/ERASE A IN ...
Page 27
... Either RP WP# HIGH unlocks the boot block Measurements tested under AC Test Condition 1, V 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY = 5V ±10%. CC Micron Technology, Inc., reserves the right to change products or specifications without notice. 27 4Mb ©2002 Micron Technology, Inc. ...
Page 28
... Notes: 1. Address inputs are “Don’t Care” but must be held stable BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F400B5 only). 3. Either RP WP# HIGH unlocks the boot block. HH 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY WRITE/ERASE CYCLE CE#-CONTROLLED WRITE/ERASE ...
Page 29
... Notes: 1. Contact factory for availability 2. All dimensions in millimeters MAX/MIN or typical where noted. 3. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY = 5V ±10 44-PIN PLASTIC SOP (600 mil) ...
Page 30
... Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY 40-PIN PLASTIC TSOP I (10mm x 20mm) .795 (20.20) .780 (19.80) ...
Page 31
... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY 48-PIN PLASTIC TSOP I (12mm x 20mm) .795 (20.20) .780 (19.80) ...
Page 32
... Rev. 2, PRELIMINARY....................................................................................................................................................12/01 • Updated input capacitance specification t • Updated RWH specification Original document, PRELIMINARY, Rev. 1....................................................................................................................7/01 09005aef8075d1f1 MT28F004B5.fm - Rev. 4, Pub. 2/2004 SMART 5 BOOT BLOCK FLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. 32 4Mb ©2002 Micron Technology, Inc. ...