MT28F320J3BS-11 MET TR Micron Technology Inc, MT28F320J3BS-11 MET TR Datasheet - Page 6
![IC FLASH 32MBIT 110NS 64FBGA](/photos/7/30/73002/557-64-fbga_sml.jpg)
MT28F320J3BS-11 MET TR
Manufacturer Part Number
MT28F320J3BS-11 MET TR
Description
IC FLASH 32MBIT 110NS 64FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT28F128J3FS-12_ET_TR.pdf
(55 pages)
Specifications of MT28F320J3BS-11 MET TR
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
32M (4Mx8, 2Mx16)
Speed
110ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
General Description
erasable (Flash), programmable memory containing
134,217,728 bits organized as 16,777,218 bytes (8 bits)
or 8,388,608 words (16 bits). This 128Mb device is
organized as one hundred twenty-eight 128KB erase
blocks.
as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).
This 64Mb device is organized as sixty-four 128KB
erase blocks.
organized as 4,194,304 bytes (8 bits) or 2,097,152 words
(16 bits). This 32Mb device is organized as thirty-two
128KB erase blocks.
They also have common Flash interface (CFI) that per-
mits software algorithms to be used for entire families
of devices. The software is device-independent, JEDEC
ID-independent with forward and backward compati-
bility.
allows a single, simple software driver in all host sys-
tems to work with all SCS-compliant Flash memory
devices. The SCS provides the fastest system/device
data transfer rates and minimizes the device and sys-
tem-level implementation costs.
device accommodates V
ing block erase, program, or lock bit configuration, or
hard-wired to V
is treated as an input pin to enable erasing, program-
ming, and block locking. When V
V
disabled. Block erase suspend mode enables the user
to stop block erase to read data from or program data
to any other blocks. Similarly, program suspend mode
enables the user to suspend programming to read data
or execute code from any unsuspended blocks.
cation programming. V
provide data protection when connected to ground.
This pin also enables program or erase lockout during
power transition.
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
CC
The MT28F128J3 is a nonvolatile, electrically block-
The MT28F640J3 contains 67,108,864 bits organized
Similarly, the MT28F320J3 contains 33,554,432 bits
These three devices feature in-system block locking.
Additionally, the scalable command set (SCS)
To optimize the processor-memory interface, the
V
PEN
lockout voltage (V
serves as an input with 2.7V or 3.3V for appli-
CC
, depending on the application. V
LKO
PEN
PEN
), all program functions are
in this Q-Flash
, which is switchable dur-
PEN
is lower than the
®
family can
PEN
6
vidual block locking that can lock and unlock a block
using the sector lock bits command sequence.
additional indicator of the internal state machine
(ISM) activity by providing a hardware signal of both
status and status masking. This status indicator mini-
mizes central processing unit (CPU) overhead and sys-
tem power consumption. In the default mode, STS acts
as an RY/BY# pin. When LOW, STS indicates that the
ISM is performing a block erase, program, or lock bit
configuration. When HIGH, STS indicates that the ISM
is ready for a new command.
and disabling the device by activating the device’s
control logic, input buffer, decoders, and sense ampli-
fiers.
read/write mode; BYTE# = 0 selects an 8-bit mode,
with address A0 selecting between the LOW and HIGH
byte, while BYTE# = 1 selects a 16-bit mode. When
BYTE# = 1, A1 becomes the lowest-order address line
with A0 being a no connect.
disabled and RP# is at V
enabled. A reset time (
switches HIGH until outputs are valid. Likewise, the
device has a wake time (
writes to the command user interface (CUI) are recog-
nized. When RP# is at GND, it provides write protec-
tion, resets the ISM, and clears the status register.
support the new security block lock features for
additional
availability.)
process
MT28F640J3 are manufactured using 0.15µm process
technology.
Micron’s even-sectored Q-Flash devices offer indi-
Status (STS) is a logic signal output that gives an
Three chip enable (CE) pins are used for enabling
BYTE# enables the device to be used in x8 or x16
RP# is used to reset the device. When the device is
Variants of the MT28F320J3 and MT28F640J3
The MT28F320J3 is manufactured using 0.18µm
Micron Technology, Inc., reserves the right to change products or specifications without notice.
technology,
code
128Mb, 64Mb, 32Mb
security.
Q-FLASH MEMORY
the
t
RWH) is required after RP#
t
RS) from RP# HIGH until
CC
MT28F128J3
, the standby mode is
(Contact
©2000 Micron Technology. Inc.
factory
and
the
for