MT48LC8M8A2TG-7E:G TR Micron Technology Inc, MT48LC8M8A2TG-7E:G TR Datasheet
![IC SDRAM 64MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC8M8A2TG-7E:G TR
Specifications of MT48LC8M8A2TG-7E:G TR
MT48LC8M8A2TG-7E:G
Related parts for MT48LC8M8A2TG-7E:G TR
MT48LC8M8A2TG-7E:G TR Summary of contents
Page 1
... Notes: 1. Refer to Micron technical note: TN-48-05. Micron Technology, Inc., reserves the right to change products or specifications without notice. 1 64Mb: x4, x8, x16 SDRAM t WR Off-center parting line. 3. Contact Micron for product availability. Part Number Example: MT48LC8M8A2TG-75:G ©2000 Micron Technology, Inc. All rights reserved. Features Marking 16M4 8M8 4M16 ...
Page 2
... MHz -75 133 MHz -7E 133 MHz -75 100 MHz Table 3: 64Mb SDRAM Part Numbers MT48LC16M4A2TG MT48LC16M4A2P MT48LC8M8A2TG MT48LC8M8A2P MT48LC4M16A2TG MT48LC4M16A2P MT48LC4M16A2B4 MT48LC4M16A2F4 Notes: 1. FBGA Device Decoder: http://www.micron.com/support/FBGA/FBGA.asp General Description The Micron containing 67,108,864 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...
Page 3
... Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. ...
Page 4
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
List of Figures Figure 1: 16 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
... ADDRESS 14 BA0, BA1 REGISTER 10 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4,096 x 1,024 x 4) DECODER SENSE AMPLIFIERS 4096 I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS ...
Page 8
... ADDRESS 14 BA0, BA1 REGISTER 9 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4,096 x 512 x 8) DECODER SENSE AMPLIFIERS 4096 I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS ...
Page 9
... ADDRESS 14 BA0, BA1 REGISTER 8 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4,096 x 256 x 16) DECODER SENSE AMPLIFIERS 4096 I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS ...
Page 10
Pin/Ball Assignments and Descriptions Figure 4: Pin Assignment (Top View) 54-Pin TSOP DQ0 - NC DQ0 DQ1 - NC NC DQ2 - NC DQ1 DQ3 - ...
Page 11
... Address inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A11) and READ/WRITE command (column-address A0–A9 [x4]; A0–A8 [x8]; A0–A7 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether all banks are to be precharged (A10[HIGH]) or bank selected by BA0, BA1 (A1[LOW]) ...
Page 12
Table 4: Pin/Ball Descriptions VFBGA TSOP Pin Ball Numbers Numbers Symbol 43, 49 A7, B3, C7 12, 46, A3, B7, C3 14, 27 A9, ...
Page 13
The recommended power-up sequence for SDRAMs: 1. Simultaneously apply power Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL- compatible. 3. Provide stable CLOCK signal. Stable clock is defined as ...
Page 14
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length READ and WRITE accesses ...
Page 15
Figure 6: Mode Register Definition M11, M10 = “0, 0” to ensure compatibility with future devices. Write Burst Mode M9 0 Programmed Burst Length 1 Single Location Access M8 M7 M6– Defined – – – Burst Type Accesses ...
Page 16
Table 5: Burst Definition Burst Length Full page (y) Notes: 1. For full-page accesses 1,024 (x4 512 (x8 256 (x16). 2. For A1–A9 (x4), A1–A8 (x8), or A1–A7 (x16) select the ...
Page 17
Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 7: CAS Latency COMMAND COMMAND Table 6: CAS Latency Operating Mode The normal operating mode is selected by setting M7 and M8 to ...
Page 18
Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following “Operation” on page 21; these tables provide current state/next state information. Table 7: ...
Page 19
... Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coin- cident with the data given DQM signal is registered LOW, the corresponding data will be written to memory ...
Page 20
A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is ...
Page 21
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE ...
Page 22
Figure 8: Activating a Specific Row in a Specific Bank A0–A10, A11 BA0, BA1 Figure 9: Example: Meeting CLK COMMAND READs READ bursts are initiated with a READ command, as shown in Figure 10 on page 23. The starting column ...
Page 23
Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be ...
Page 24
Figure 11: CAS Latency COMMAND COMMAND PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CLK READ NOP CLK READ NOP 64Mb: x4, ...
Page 25
Figure 12: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CLK READ NOP NOP BANK, COL n ...
Page 26
Figure 13: Random READ Accesses COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ ...
Page 27
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 14 shows the case where the clock frequency allows for bus ...
Page 28
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full- page burst may be truncated with a PRECHARGE command to the same ...
Page 29
Figure 17: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30. The starting column and bank addresses are provided with ...
Page 30
An example is shown in Figure 20 on page 31. Data either the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore ...
Page 31
Figure 20: WRITE-to-WRITE CLK COMMAND ADDRESS TRANSITIONING DATA Note: DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst ...
Page 32
Figure 21: Random WRITE Cycles CLK COMMAND ADDRESS Note: Each WRITE command may be to any bank. DQM is LOW. Figure 22: WRITE-to-READ CLK COMMAND ADDRESS Note: The WRITE command may be to any bank, and the READ command may ...
Page 33
Figure 23: WRITE-to-PRECHARGE CLK CLK ≥ 15ns DQM COMMAND ADDRESS CLK < 15ns DQM COMMAND ADDRESS Note: DQM could remain LOW in this example if the WRITE burst is a fixed length ...
Page 34
Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs ...
Page 35
Figure 26: Power-Down CLK CKE COMMAND All banks idle Enter power-down mode. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is ...
Page 36
Figure 27: Clock Suspend During WRITE Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Figure 28: Clock Suspend During READ Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Note: For this example greater, and DQM ...
Page 37
READ with Auto Precharge • Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to ...
Page 38
Figure 30: READ With Auto Precharge Interrupted by a WRITE Internal States Notes: 1. DQM is HIGH prevent D Figure 31: WRITE With Auto Precharge Interrupted by a READ Internal States Notes: 1. DQM is LOW. PDF: ...
Page 39
Figure 32: WRITE With Auto Precharge Interrupted by a WRITE Internal States Notes: 1. DQM is LOW. Table 8: Truth Table 2 – CKE Notes 1–4 apply to entire table CKE CKE Current State n Power-Down Self ...
Page 40
Table 9: Truth Table 3 – Current State Bank n, Command to Bank n (Notes 1–6 apply to entire table; notes appear below and on next page) Current State CS# RAS# Any Idle ...
Page 41
Accessing mode Precharging all: Starts with registration of a PRECHARGE ALL command and ends when 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not ...
Page 42
Table 10: Truth Table 4 – Current State Bank n, Command to Bank m (Notes 1–6 apply to entire table; notes appear below and on next page) Current State CS# RAS# Any Idle X X Row ...
Page 43
All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. ...
Page 44
Electrical Specifications Stresses greater than those listed in Table 11 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
Page 45
Table 12: Temperature Limits Parameter Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figure 33 ...
Page 46
Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN 22.22mm 11.11mm 8.00mm 4.00mm 8.00mm ...
Page 47
Table 14: DC Electrical Characteristics and Operating Conditions Notes apply to entire table; notes appear on pages 50 and 51; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All ...
Page 48
Table 18: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 34 apply to entire table; notes appear on pages 50 and 51 Characteristics Parameter Access time from CLK (positive edge) ...
Page 49
Table 19: AC Functional Characteristics Notes 11, 34 apply to entire table; notes appear on pages 50 and 51; V Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to ...
Page 50
Notes 1. All voltages referenced This parameter is sampled. V biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used ...
Page 51
V IH cannot be greater than one-third of the cycle rate pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock ...
Page 52
Timing Diagrams Figure 35: Initialize and Load Mode Register CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ...
Page 53
Figure 36: Power-Down Mode T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active ...
Page 54
Figure 37: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM / DQML, DQMH ...
Page 55
Figure 38: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ ...
Page 56
Figure 39: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge ...
Page 57
Figure 40: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW ...
Page 58
Figure 41: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE ...
Page 59
Figure 42: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ...
Page 60
Figure 43: Single READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0–A9, A11 ROW ...
Page 61
Figure 44: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE AUTO ...
Page 62
Figure 45: READ – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 ...
Page 63
Figure 46: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO ...
Page 64
Figure 47: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW ...
Page 65
Figure 48: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, ...
Page 66
Figure 49: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ...
Page 67
Figure 50: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW t ...
Page 68
Figure 51: Alternating Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, A11 ROW ...
Page 69
Figure 52: WRITE – Full-Page Burst CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 ...
Page 70
Figure 53: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 t AS ...
Page 71
Package Dimensions Figure 54: 54-Pin Plastic TSOP II (400 mil) PIN # 0. 1.00 10.16 ±0.08 11.76 ±0.20 +0.03 0.15 -0.02 Notes: 1. All dimensions are in millimeters. 2. Package width and length do not ...
Page 72
Figure 55: 54-Ball VFBGA “F4/B4” Package, 8mm x 8mm 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0.42. BALL A9 6.40 3.20 3.20 Notes: 1. ...