AT26DF161A-MU Atmel, AT26DF161A-MU Datasheet - Page 3

• Manufacturer Part Number: AT26DF161A-MU
• Description: IC FLASH 16MBIT 70MHZ 8QFN
• Manufacturer: Atmel

Specifications of AT26DF161A-MU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (8192 pages x 256 bytes)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Pin Descriptions and Pinouts
Table 2-1.
3640D–DFLASH–8/09
Symbol
CS
SCK
SI
SO
WP
HOLD
V
GND
CC
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
section
and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to section
on page 30
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to V
possible.
DEVICE POWER SUPPLY: The V
Operations at invalid V
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
Pin Descriptions
“Protection Commands and Features” on page 15
for additional details on the Hold operation.
Figure 2-1.
CC
voltages may produce spurious results and should not be attempted.
GND
WP
SO
CS
CC
8-SOIC Top View
1
2
3
4
pin is used to supply the source voltage to the device.
8
7
6
5
VCC
HOLD
SCK
SI
for more details on protection features
Figure 2-2.
CC
GND
whenever
WP
SO
CS
8-MLF Top View
1
2
3
4
“Hold”
CC
8
7
6
5
Asserted
State
VCC
HOLD
SCK
SI
Low
Low
Low
Output
Power
Power
Type
Input
Input
Input
Input
Input
3