AT45DB041D-SSU Atmel, AT45DB041D-SSU Datasheet - Page 10

• Manufacturer Part Number: AT45DB041D-SSU
• Description: IC FLASH 4MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB041D-SSU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 4Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 8
• Memory Configuration: 2048 Pages X 256 Bytes
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7-2.
7.7
10
PA10/
A18
0
0
0
0
1
1
1
1
•
•
•
Chip Erase
AT45DB041D
PA9/
A17
0
0
0
1
0
0
1
1
•
•
•
Sector Erase Addressing
PA8/
A16
(1)
0
0
1
0
0
1
0
1
•
•
•
The entire main memory can be erased at one time by using the Chip Erase command.
To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH
must be clocked into the device. Since the entire memory array is to be erased, no address
bytes need to be clocked into the device, and any data clocked in after the opcode will be
ignored. After the last bit of the opcode sequence has been clocked in, the CS pin can be deas-
serted to start the erase process. The erase operation is internally self-timed and should take
place in a time of t
The Chip Erase command will not affect sectors that are protected or locked down; the contents
of those sectors will remain unchanged. Only those sectors that are not protected or locked
down will be erased.
The WP pin can be asserted while the device is erasing, but protection will not be activated until
the internal erase cycle completes.
Figure 7-1.
Note:
Command
Chip Erase
PA7/
A15
X
X
X
X
X
X
0
0
•
•
•
1. Refer to the errata regarding Chip Erase on
PA6/
A14
X
X
X
X
X
X
0
0
•
•
•
Chip Erase
CS
SI
CE
. During this time, the Status Register will indicate that the device is busy.
PA5/
A13
X
X
X
X
X
X
0
0
Each transition
represents 8 bits
•
•
•
PA4/
A12
Opcode
Byte 1
X
X
X
X
X
X
0
0
•
•
•
PA3/
A11
X
X
X
X
X
X
0
1
Byte 1
•
•
•
C7H
Opcode
Byte 2
PA2/
A10
X
X
X
X
X
X
X
X
page
•
•
•
Opcode
Byte 3
54.
Byte 2
94H
PA1/
A9
X
X
X
X
X
X
X
X
•
•
•
Opcode
Byte 4
PA0/
A8
X
X
X
X
X
X
X
X
•
•
•
Byte 3
80H
3595P–DFLASH–09/09
Sector
0a
0b
1
2
4
5
6
7
•
•
•
Byte 4
9AH