AT25DF321-SU Atmel, AT25DF321-SU Datasheet - Page 22

• Manufacturer Part Number: AT25DF321-SU
• Description: IC FLASH 32MBIT 70MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF321-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (16384 pages x 256 Bytes)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1.6
10.2
22
Write Status Register
AT25DF321
RDY/BSY Bit
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts
due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is
deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire
opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-
mand must have been clocked into the device.
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program
or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase
cycle, new Status Register data must be continually clocked out of the device until the state of
the RDY/BSY bit changes from a logical “1” to a logical “0”.
Figure 10-1. Read Status Register
The Write Status Register command is used to modify the SPRL bit of the Status Register
and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-
ter command can be issued, the Write Enable command must have been previously issued to
set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register command, the CS pin must first be asserted and the opcode
of 01h must be clocked into the device followed by one byte of data. The one byte of data con-
sists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or
Unprotect should be performed, and two additional don’t care bits (see
tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the
SPRL bit in the Status Register will be modified and the WEL bit in the Status Register will be
reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before
the Write Status Register command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global
Protect/Unprotect” section on
• Write Disable operation completes successfully
• Write Status Register operation completes successfully or aborts
• Protect Sector operation completes successfully or aborts
• Unprotect Sector operation completes successfully or aborts
• Byte/Page Program operation completes successfully or aborts
• Block Erase operation completes successfully or aborts
• Chip Erase operation completes successfully or aborts
SCK
CS
SO
SI
MSB
HIGH-IMPEDANCE
0
0
0
1
0
2
OPCODE
0
3
0
page 15
4
1
5
0
6
1
7
for more details.
MSB
D
STATUS REGISTER DATA
8
D
9
D
10 11
D
D
12
D
13 14
D
D
15 16
MSB
D
STATUS REGISTER DATA
D
17
D
18
D
19
D
20
Table
D
21 22
D
D
23 24
10-2). Any addi-
3669B–DFLASH–6/09
MSB
D
D