AT24C32CY6-YH-T Atmel, AT24C32CY6-YH-T Datasheet - Page 6

• Manufacturer Part Number: AT24C32CY6-YH-T
• Description: IC EEPROM 32KBIT 1MHZ 8DFN
• Manufacturer: Atmel

Specifications of AT24C32CY6-YH-T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 32K (4K x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UDFN Exposed Pad
• Organization: 4 K x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 1 MHz
• Access Time: 550 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT24C32CY6-YH-TTR

4. Device Operation
Figure 4-1.
6
SCL
SDA
AT24C32C/64C
Software Reset
Start bit
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Data Valid-
ity timing diagram). Data changes during SCL high periods will indicate a start or stop condition
as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C32C/64C features a low power standby mode which is enabled:
a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire
part can be protocol reset by following these steps:
(a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit
condition as shown below. The device is ready for next communication after above steps have
been completed.
1
2
Dummy Clock Cycles
3
8
9
Start bit
5298A–SEEPR–1/08
Stop bit