AT45DB321C-CNU Atmel, AT45DB321C-CNU Datasheet - Page 5

• Manufacturer Part Number: AT45DB321C-CNU
• Description: IC FLASH 32MBIT 40MHZ 8CASON
• Manufacturer: Atmel

Specifications of AT45DB321C-CNU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (8192 pages x 528 bytes)
• Speed: 40MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-CASON
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.1.2
5.1.3
5.2
5.2.1
3387M–DFLASH–2/08
Program and Erase Commands
Main Memory Page Read
Buffer Read
Buffer Write
A main memory page read allows the user to read data directly from any one of the 8192 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read, an opcode of D2H must be clocked into the device. The
opcode is followed by three address bytes (which comprise 24-bit page and byte address
sequence) and 32 don’t care clock cycles. The first bit of the 24-bit address sequence is a
reserved bit, the next 13 bits (PA12-PA0) of the 24-bit address sequence specify the page in
main memory to be read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify
the starting byte address within that page. The 32 don’t care clock cycles that follow the three
address bytes are sent to initialize the read operation. Following the don’t care bytes, additional
pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain
low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of
data. When the end of a page in main memory is reached, the device will continue reading back
at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read
operation and tristate the output pin (SO). The maximum SCK frequency allowable for the Main
Memory Page Read is defined by the f
both data buffers and leaves the contents of the buffers unchanged.
Data can be read from either one of the two buffers, using different opcodes to specify which
buffer to read from. An opcode of D4H is used to read data from buffer 1, and an opcode of D6H
is used to read data from buffer 2. To perform a buffer read, the opcode must be clocked into the
device followed by three address bytes comprised of 14 don’t care bits and 10 buffer address
bits (BFA9-BFA0). Following the three address bytes, an additional don’t care byte must be
clocked in to initialize the read operation. Since the buffer size is 528 bytes, 10 buffer address
bits are required to specify the first byte of data to be read from the buffer. The CS pin must
remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the
reading of data. When the end of a buffer is reached, the device will continue reading back at the
beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation
and tristate the output pin (SO).
Data can be clocked in from the SI pin into either buffer 1 or buffer 2. To load data into either
buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, fol-
lowed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9-
BFA0). The 10 buffer address bits specify the first byte in the buffer to be written. After the last
address byte has been clocked into the device, data can then be clocked in on subsequent clock
cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning
of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is
detected on the CS pin.
SCK
specification. The Main Memory Page Read bypasses
AT45DB321C
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