AT88SC6416C-CI Atmel, AT88SC6416C-CI Datasheet - Page 5

• Manufacturer Part Number: AT88SC6416C-CI
• Description: IC EEPROM 64KBIT 1.5MHZ 8LAP
• Manufacturer: Atmel
• Series: CryptoMemory®r

Specifications of AT88SC6416C-CI

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 5MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-LAP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Protocol Selection
Asynchronous
T = 0 Protocol
Synchronous
2-wire Serial Interface
5015CS–SMEM–6/04
The AT88SC6416C supports two different communication protocols.
•
•
The power-up sequence determines which of the two communication protocols will be
used.
This power-up sequence complies with ISO 7816-3 for a cold reset in smart card
applications.
•
•
•
•
The device will respond with a 64-bit ATR code, including historical bytes to indicate the
memory density within the CryptoMemory family. Once the asynchronous mode has
been selected, it is not possible to switch to the synchronous mode without powering off
the device.
Figure 2. Asynchronous T = 0 Protocol
After a successful ATR, the Protocol and Parameter Selection (PPS) protocol, as defined
by ISO 7816-3, may be used to negotiate the communications speed with CryptoMemory
devices 32 Kbits and larger. CryptoMemory supports D values of 1, 2, 4, 8, 12, and 16 for
an F value of 372. Also supported are D values of 8 and 16 for F = 512. This allows selec-
tion of 8 communications speeds ranging from 9600 baud to 153,600 baud.
The synchronous mode is the default after powering up V
on RST. For embedded applications using CryptoMemory in standard plastic packages,
this is the only communication protocol.
•
•
Figure 3. Synchronous 2-wire Protocoll
Note:
Smart Card Applications: The asynchronous T = 0 protocol defined by ISO 7816-3
is used for compatibility with the industry’s standard smart card readers.
Embedded Applications: A 2-wire serial interface is used for fast and efficient
communication with logic or controllers.
V
Set I/O-SDA in receive mode.
Provide a clock signal to CLK-SCL.
RST goes high after 400 clock cycles.
Power-up V
After stable V
CLK-SCL
CC
I/O-SDA
CLK-SCL
I/O-SDA
Five clock pulses must be sent before the first command is issued.
goes high; RST, I/O-SDA and CLK-SCL are low.
RST
V cc
RST
V cc
CC
CC
, RST goes high also.
, CLK-SCL and I/O-SDA may be driven.
1
2
3
4
5
CC
AT88SC6416C
due to the internal pull-up
ATR
5